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LAUNCHXL-F28P65X: EtherCAT communication with CPU2

Huanli Liu
Prodigy 20 points

Part Number: LAUNCHXL-F28P65X
Other Parts Discussed in Thread: C2000WARE

Hi engineers,

We have a LAUNCHXL-F28P65X for EtherCAT testing. With the solution described in

"">e2e.ti.com/.../launchxl-f28p65x-unable-to-scan-for-the-device-by-twincat",

EtherCAT works fine after we replaced the PHY chip. The code for our test is:

"C:\ti\c2000\C2000Ware_5_01_00_00\libraries\communications\Ethercat\f28p65x\examples\f28p65x_cpu1_echoback_solution"

This project uses only CPU1. We have used the FLASH build option, so it all works fine even when re-powered. However, when we tested EtherCAT communication using CPU2, it did not work properly, here is our complete test procedure, which you should easily be able to reproduce it.

1. Software Version

CCS：12.5.0.00007 

C2000Ware：C2000Ware_5_01_00_00

TwinCAT Version：v3.1.4024.12

SSC Version: 5.12

Sample project location：***\C2000Ware_5_01_00_00\libraries\communications\Ethercat\f28p65x\examples\f28p65x_cpu2_echoback_solution

2. Description of the problem

Generate EtherCAT stack source code using SSC and import f28p65x_cpu2_echoback_solution project:

Both projects switch to FLASH build and add the _LAUNCHXL_F28P65X macro definition:

Add EterhCAT stack source path to ensure proper compilation for f28p65x_cpu2_echoback_solution project:

After compilation, the following information is obtained for f28p65x_cpu1_allocate_ecat_to_cpu2 and f28p65x_cpu2_echoback_solution:

In order to ensure that the download into FLASH is done correctly, the following configuration is added for f28p65x_cpu1_allocate_ecat_to_cpu2:

After the download is complete, click on CPU1's project to run first, then click on CPU2's project to run:

Copy the generated xml file from SSC to "C:\TwinCAT\3.1\Config\Io\EtherCAT" and reopen TwinCAT to start the scan:

Although the device can be scanned, after clicking OK, CPU2 indicates that it has entered the illegal error:

Meanwhile TwinCAT is not able to enter the OP state:

Therefore, we would like to ask if the f28p65x_cpu2_echoback_solution project is working properly? Is it that we missed some critical steps?

How can we fix this if you can reproduce it too?

Thanks!

  • +1
    Prodigy 20 points

    Problem solved. The key is the order of download. Consider that GSRAM permissions have not been assigned to cpu2 before running the cpu1 program. So we need to download cpu1's program first and run, then download cpu2's program and run afterwards and it will work. The following are the key steps:

    1. Load the program for cpu1 and run;

    2. Make sure the cpu2 core is not connected;

    3. Connect the cpu2 core and load the program for cpu2;

    4. Run cpu2 and the project should work.