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TMS320F28388D: EPWM1 are defined and Initialized in CPU1, and ePWM1 interrupt configuration is conducted in CPU1 and CPU2, both of them can enter the ePWM1 interrupt, Does the ePWM1 interrupt in CPU2 running properly and Sync with the ePWM1 interrupt in CP

Zhong Wang
Prodigy 10 points
Part Number: TMS320F28388D

Tool/software:

EPWM1 are defined and Initialized in CPU1, and ePWM1 interrupt configuration is conducted in CPU1 and CPU2, both of them can enter the ePWM1 interrupt, Does the ePWM1 interrupt in CPU2 running properly and Sync with the ePWM1 interrupt in CPU1.

  • 0
    TI__Mastermind 18680 points

    Hi Zhong,

    There is no guarantee the CPU1 and CPU2 ISRs will execute simultaneously. The interrupt flag will be set in the PIE for each CPU simultaneously, but CPU1 and/or CPU2 could be servicing other interrupts that delay the entering of the ISR.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 10 points

    Hi Luke,

    The ePWM1 interrupt in CPU1 was defined as the highest priority ISR in CPU1, and the ePWM1 interrupt in CPU2 was defined as the highest priority ISR in CPU2, Does the two ePWM1 interrupt execute simultaneously?

    Thank you,

    Zhong

  • +1 in reply to Zhong Wang
    TI__Mastermind 18680 points

    Hi Zhong,

    Unless interrupt nesting is enabled, even the highest priority interrupts will be stalled by any other interrupt that is currently executing. This will cause the EPWM ISRs on CPU1 and CPU2 to become out of sync if any other ISRs are executing on either CPU when the EPWM interrupt gets triggered.