LAUNCHXL-F28P55X: F28P55X

Basically, clock strech is not seen for software to send NACK ..

Hi Hari,

NACKs are typically used to specifically detect erroneous messages within PMBus HW. In order to NACK, the PMBACK must have a zero written to it and can only be done when the module is waiting for an acknowledgement. If the bit is written to at any other time, the NACK occurs the next message. When reading PMBSTS.NACK, when does this bit get set? In what condition, should the PMBus send a NACK?

If you want to clock stretch, take a look at the PMBSTS.DATA_REQUEST/DATA_READY register values. The PMBus module already takes care of stretching the clock until an ACK is issued, so in this scenario, it looks like you need to add some sort of delay so the clock is held low. 

Best Regards,

Aishwarya

Hi Aishwarya,

Thanks for the reply. My scenario is to implement NACK when a command is received with invalid data bitfields. Yes, I am writing PMBACK register.

In fact, the code is the same example code in C2000WARE - C2000Ware_5_02_00_00\libraries\communications\PMBus\c28\examples\28p55x_pmbus_target.

All I did is take the pmbus_stack_handler_target_idle.c and change 

//
// Call the handler for the SENDBYTE transaction
//
(void)handle->
transactionHandle[PMBUS_TRANSACTION_SENDBYTE](handle);

//
// ACK the entire transaction
//
PMBus_nackTransaction(base); <-- I changed it to NACK

On compile and testing, NACK was not seen ; in fact every other frame is NACK'd. the snap of i2c analyser is in my previous message. 

Do you think i need the probe the PMBACK with gpio ? The ACK slot is missed and sent to next message ??

Hari,

What happens if you use the PMBus_ackTransaction() instead? PMBus takes care of NACKs in the hardware, so even if you try to ACK a wrong transaction, it should return a NACK instead. Please refer to these threads as a starting point, I'll do some digging around in the mean time: 

(+) TMS320F280039C: Manual ACK/NACK of Slave address of PMBus module issue

(+) TMS320F280025C: PMBUS do not sent ACK when restart command?

Best Regards,

Aishwarya

aishwarya,

I see an ACK when PMBus_ackTransaction() is used. Here,in below snap, i have toggled the gpio first) when irq is received second) when ack PMBACK is written to nack. As you see, the irq comes only after the ACK Slot. if this is case, how will NACK , why the device is not clock streching untill firmware writes the PMBACK register ?

My init is as follows,

void myPMBUS0_init(){
uint32_t moduleFreq = 0U;
PMBus_disableModule(myPMBUS0_BASE);
PMBus_disableI2CMode(myPMBUS0_BASE);
PMBus_disableZeroHoldTime(myPMBUS0_BASE);
PMBus_deassertAlertLine(myPMBUS0_BASE);
PMBus_setOwnAddress(myPMBUS0_BASE, myPMBUS0_OWN_ADDRESS);
moduleFreq = PMBus_configModuleClock(myPMBUS0_BASE, myPMBUS0_BAUDRATE, DEVICE_SYSCLK_FREQ);
PMBus_configBusClock(myPMBUS0_BASE, myPMBUS0_CLOCKMODE, moduleFreq);

PMBus_initTargetMode(myPMBUS0_BASE, myPMBUS0_TARGET_ADDRESS, myPMBUS0_TARGET_ADDRESS_MASK);
PMBus_configTarget(myPMBUS0_BASE, /* PMBUS_TARGET_AUTO_ACK_4_BYTES |*/ PMBUS_TARGET_ENABLE_PEC_PROCESSING);
PMBus_disableInterrupt(myPMBUS0_BASE, PMBUS_INT_DATA_READY | PMBUS_INT_DATA_REQUEST | PMBUS_INT_EOM);
PMBus_enableInterrupt(myPMBUS0_BASE, PMBUS_INT_DATA_READY | PMBUS_INT_DATA_REQUEST | PMBUS_INT_EOM);
PMBus_enableModule(myPMBUS0_BASE);
}

How would i make the device clock stretch untill a ACK/NACK is written into the PMBACK register ?

Hari,

According to the image you attached, after the ACK, the module is pulling the data line low and releasing the clock which is correct and consistent with your code. Are you using the Write Word/Byte function? Refer to this image especially the highlighted part.

Also, writing a zero to the PMBACK bit sends a NACK only while the module is waiting for an acknowledgement. Otherwise, the NACK will be sent during the next message FYI  

Refer to the I2C Automatic Clock Stretching section (similar principle applies to PMBus) as well for general idea if you are interested.  

Best Regards,

Aishwarya 

Hari,

Have you been able to resolve this issue? If there are no more questions, I will go ahead and close this thread  

Best Regards,

Aishwarya 

Aishwarya,

I was not able to figure out still.

I understand that ACK has to be provided at the ACK Slot but the interrupt to the device firmware comes at stop bit .. how am i supposed to write PMBACK bit  during ACK/NACK Slot when interrupt itself is sent on stop bit? 

Hari,

I believe what is happening is that because the option to auto ACK after every 4 bytes is enabled, the PMBus hardware is taking care of ack/nack based on default PMBus ack/NACK rules (info found in TRM). When you are NACKing at the end of the first transmission, you are NACKing all the following commands since the opportunity to set the NACK of first transmission is over and this is breaking the auto ack setting already set. This is consistent with I2C since they do share the same basic design layer.

What you want to do is use manual ACK/NACK, so that an interrupt is fired right after x amount of data bytes are sent and before the ACK/NACK slot. 

Best Regards,

Aishwarya