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TMS320F28035: TMS320F28035

Enzo Ternavasio
Intellectual 935 points
Part Number: TMS320F28035
Other Parts Discussed in Thread: MSP430F5171,

Tool/software:

Using MSp430F5171 to acquire continously from an AD converter with SPI bus, i have seen that some disurbance can occur on data when oher devices, connected to the same SPI, interupt this process, to be serviced.

TMS320F28035 has 2 SPI channels. Can this micro service one SPI in an indipendent way from the other? In other words, the acquisiton process from AD based on SPI A is not disturbed in any way by an interrupt from other device, requesting the other SPI B bus?

Enzo - Dolang Italy

  • 0
    TI__Genius 14360 points

    Hi Enzo,

    Apologies for the delay. Please allow for another day for me to review this inquiry. Thanks for the patience!

    Best Regards,

    Allison

  • 0
    TI__Genius 14360 points

    Hi Enzo,

    Only one interrupt can be handled by the CPU at once (one line feeding into the CPU as per below from the device TRM). And if you do not nest interrupts (nesting is not allowed by default), then an interrupt that is in progress will never by cut off by another new incoming interrupt. The first interrupt would finish first before entering the next.

    If you specifically are saying you do not want SPIA interrupts to be masked by SPIB interrupts, then you just need to make sure that SPIA has higher priority interrupts than SPIB so that SPIA interrupts are always taken first over SPIB. This is the case as seen in the TRM as well (SPIA is INT6.1 and INT6.2; SPIB is INT6.3 and INT6.4):

    But if you are asking if the two SPI modules can operate completely independently (interrupt-wise), the interrupt architecture does not support two simultaneous interrupts if SPIA and SPIB interrupts were to occur at the same time unless you use a device with separate CPUs.

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Intellectual 935 points

    Hy Allison, thanks for your reply.

    I mean that if SPI A is working (trasmiting or receiving) and an interrupt routine is in the same time working with SPI B, is the SIMO, SOMI, CLK line of SPI A disturbed?

  • +1 in reply to Enzo Ternavasio
    TI__Genius 14360 points

    Hi Enzo,

    SPI module operation (transmit and receive) on two separate SPI modules can occur at the same time without interfering data transmission - they operate independently. The only interference between two SPI modules is if/when you have interrupt service routines to read the data. In that case, the CPU can only handle one interrupt at a time, so that's when you have to be conscious of the timing of the interrupts. But, for example, you could implement FIFO mode so that the data accumulates in the FIFO if for some reason other interrupts delay the interrupt used to read the data.

    Best Regards,

    Allison