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TMS320F28377S: 320F2837x - SPI Module SPISTE Control

Paul Hetherington
Prodigy 150 points
Part Number: TMS320F28377S

Tool/software:

TMS320F28377S - SPI module

How exactly does the Master set/clear SPISTE? Is there a control bit in a register?

Technical Reference Manual - TMS320F2837xS

17.4.4 Data Transfer Example - seems to indicate that SPISTE is controlled via DSP firmware directly.

A Slave writes 0D0h to SPIDAT and waits for the master to shift out the data.
B Master sets the slave SPISTE signal low (active).
C Master writes 058h to SPIDAT, which starts the transmission procedure.
D First byte is finished and sets the interrupt flags.
E Slave reads 0Bh from its SPIRXBUF (right-justified).
F Slave writes 04Ch to SPIDAT and waits for the master to shift out the data.
G Master writes 06Ch to SPIDAT, which starts the transmission procedure.
H Master reads 01Ah from the SPIRXBUF (right-justified).
I Second byte is finished and sets the interrupt flags.
J Master reads 89h and the slave reads 8Dh from their respective SPIRXBUF. After the user’s software masks off the
unused bits, the master receives 09h and the slave receives 0Dh.
K Master clears the slave SPISTE signal high (inactive).

  • 0
    TI__Mastermind 20880 points

    Hi Paul, 

    There is no bit to set SPISTE high/low. If that GPIO is initialized/configured as the SPISTE, then the SPISTE activity is controlled inherently by the SPI hardware. The datasheet lists the timings details for this as well.

    You can alternatively manually control a GPIO as the chip select pin by making the pin an output and manually writing it low/high before/after communication transmission.

    Best Regards,

    Allison

  • 0
    Prodigy 150 points

    Hi Allison,

    Thank you for your response. Follow up question:

    For a multi char master transmission, is it possible to arrange for the SPI hw to keep SPISTE active during the entire transmission? We don't want it to go inactive between chars. Is so, how to accomplish this?

    Thanks,

    Paul

  • 0 in reply to Paul Hetherington
    TI__Mastermind 20880 points

    Hi Paul,

    The SPISTE hardware will behave based on the timings in the datasheet section. There is a note in those diagrams as well:

    Essentially, if there is time between data transmissions, the STE will go high in between. If this is the case, but you want it to remain low (active state), you would then have to control it manually as a GPIO output rather than using the dedicated SPISTE signal/hardware. 

    Otherwise, if you send direct back-to-back transmissions, STE will remain low the whole time.

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Prodigy 150 points

    Hi Allison,

    Thanks again.

    How does the code guarantee that transmissions are back-to-back? In FIFO mode, in non-FIFO mode.

    Paul

  • +1 in reply to Paul Hetherington
    TI__Mastermind 20880 points

    Hi Paul,

    What this means is you need to keep the SPI transmit buffer full. In both FIFO and non-FIFO mode, the second 16-bit word must be written to TXBUF before the first word completes transmission.  This will eliminate the gap between transmit words, and keep SPISTE pulled low the entire time.

    For this reason, utilizing FIFO mode may be easier so that you can fill up the TX FIFO and let the hardware constantly shift data out (keeping STE low).

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Prodigy 150 points

    Thanks Allison! Thats the info I couldn't find in the data sheet.