LAUNCHXL-F28379D: LAUNCHXL-F28379D: Inquiry about synchronization of 2 epwm using 2 cmpss and trip zone

JUNYEONG OH

Tool/software:

Dear Team.

We are trying to receive a sinusoidal signal as cmpss1 and 2 and generate synchronized epwm duty according to the reference value set by register bits DACHVALS.bit.DACVAL and DACLVALS.bit.DACVAL using the same trip zone.
EPWM1 is set to enable DCA EVENT1, and EPWM2 is set to enable DCA EVENT2.
There are two reference values. For cmpss1, if it exceeds 2.5V above the 3.3V standard, a trip zone is triggered to create a synchronized epwm. For cmpss2, when it falls below 0.8V below the 3.3V standard, a trip zone is triggered to generate a synchronized epwm.
When the trip zone is triggered using only cmpss1 and epwm1, synchronized epwm1 is generated well. However, when the trip zone is triggered when using cmpss1 and 2, the EPWM1 waveform seems to come out well, but EPWM2 does not come out well.
Is there a way to simultaneously output waveforms synchronized to the two reference voltages generated by DACHVALS.bit.DACVAL and DACLVALS.bit.DACVAL?

In order to use cmpss1 and 2 at the same time, is there any part of the code that needs to be set differently?

Perhaps because the same dacaRegs are used, the waveform appears similar no matter which of the two pins cmpss1 or cmpss2 is input.
Is it okay for the development board to input the same signal to cmpss1 and cmpss2 at the same time?

Sincerely,
Junyeong Oh

7 months ago

0 Allison Nguyen 7 months ago

TI__Mastermind 20630 points

Hi Junyeong,

Can you send a snippet of your EPWM1 and EPWM2 initializations so I can take a look? I want to check the trip zone registers particularly.

Best Regards,

Allison

0 JUNYEONG OH 7 months ago in reply to Allison Nguyen

Prodigy 40 points

Hi Allison

The code below is the initialization code of EPWM1 and EPWM2.

EALLOW;
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0x3;
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x3;
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2;
EPwm1Regs.TZDCSEL.bit.DCBEVT1 = 2;
EPwm1Regs.TZSEL.bit.DCAEVT1 = 1; // DCA EVENT1 Enable
EPwm1Regs.TZSEL.bit.DCBEVT1 = 1; // DCB EVENT1 Enable
EPwm1Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;
EPwm1Regs.TZCTL.bit.DCBEVT1 = TZ_NO_CHANGE;
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0; // Source is DCAEVT1 Signal
EPwm1Regs.DCBCTL.bit.EVT1SRCSEL = 0; // Source is DCBEVT1 Signal
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; // Source is Asynchronous Signal
EPwm1Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 1; // Source is Asynchronous Signal
EDIS;

EALLOW;
// EPWM Mode Setting
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

EPwm1Regs.TBPRD = PWM_PRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

EPwm1Regs.CMPA.bit.CMPA = PWM_PRD/2;
EPwm1Regs.CMPB.bit.CMPB = PWM_PRD/2;

// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and douwn
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM1A on event A, down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count

//Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = 0x3;
EPwm1Regs.DBCTL.bit.POLSEL = 0x2;
EPwm1Regs.DBCTL.bit.IN_MODE = 0x3;
EPwm1Regs.DBCTL.bit.OUTSWAP = 0x0;
EPwm1Regs.DBCTL.bit.DEDB_MODE = 0x0;

EPwm1Regs.DBRED.all = deadtime;
EPwm1Regs.DBFED.all = deadtime;

// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO; // equal to zero or period (TBCTR = 0 or TBCTR = TBPRD)
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm1Regs.TZEINT.bit.DCAEVT1 = 1; // EPWM1_TZ_ISR Enable by CMPSS
EPwm1Regs.TZEINT.bit.DCBEVT1 = 1; // EPWM1_TZ_ISR Enable by CMPSS
EDIS;

EALLOW;
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0x3;
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x3;
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 2; // DCAH = high, DCAL = don't care => DCA Event2
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = 2; // DCBH = high, DCBL = don't care => DCB Event2
EPwm2Regs.TZSEL.bit.DCAEVT2 = 1;
EPwm2Regs.TZSEL.bit.DCBEVT2 = 1;
EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_NO_CHANGE;
EPwm2Regs.TZCTL.bit.DCBEVT2 = TZ_NO_CHANGE;
EPwm2Regs.DCACTL.bit.EVT2SRCSEL = 0; // Source is DCAEVT2 Signal
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = 0; // Source is DCBEVT2 Signal
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 1; // Source is Asynchronous Signal
EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 1; // Source is Asynchronous Signal
EDIS;

EALLOW;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

// EPWM Mode Setting
EPwm2Regs.TBPRD = PWM_PRD; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter

EPwm2Regs.CMPA.bit.CMPA = PWM_PRD/2;
EPwm2Regs.CMPB.bit.CMPB = PWM_PRD/2;

// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and douwn
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading

EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM2A on event A, down count
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM2B on event B, up count
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM2B on event B, down count

//Setup Deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = 0x3;
EPwm2Regs.DBCTL.bit.POLSEL = 0x2;
EPwm2Regs.DBCTL.bit.IN_MODE = 0x3;
EPwm2Regs.DBCTL.bit.OUTSWAP = 0x0;
EPwm2Regs.DBCTL.bit.DEDB_MODE = 0x0;

EPwm2Regs.DBRED.all = deadtime;
EPwm2Regs.DBFED.all = deadtime;

EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO; // equal to zero or period (TBCTR = 0 or TBCTR = TBPRD)
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm2Regs.TZEINT.bit.DCAEVT2 = 1;
EPwm2Regs.TZEINT.bit.DCBEVT2 = 1;

EDIS;

EALLOW;
EPwmXbarRegs.TRIP4MUX0TO15CFG.all = 0x0000;
EPwmXbarRegs.TRIP4MUX16TO31CFG.all = 0x0000;
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 1;
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1; // CMPPS1L or CMPPS1H Enable
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 1;
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1; // CMPPS2L or CMPPS2H Enable
EPwmXbarRegs.TRIPOUTINV.bit.TRIP4 = 0;
Cmpss1Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
Cmpss1Regs.COMPSTSCLR.bit.LLATCHCLR = 1;
Cmpss2Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
Cmpss2Regs.COMPSTSCLR.bit.LLATCHCLR = 1;
EDIS;

Sincerely,

Junyeong Oh

0 Allison Nguyen 7 months ago in reply to JUNYEONG OH

TI__Mastermind 20630 points

Hi Junyeong,

Thanks for the above. Please allow another day for me to review the PWM trip and related configurations and check with a CMPSS expert on any further input.

Best Regards,

Allison

0 Allison Nguyen 7 months ago in reply to Allison Nguyen

TI__Mastermind 20630 points

Hi Junyeong,

Some items I wanted to verify first when reviewing your EPWM1 vs. EPWM2 configurations:

EPWM1
- Phase shift is enabled
- You are using DCAEVT1 and DCBEVT1 for your EPWM1 trips
  - Digital Compare 1 events are used for one-shot trips
EPWM2
- Phase shift is disabled
- You are using DCAEVT2 and DCBEVT2 for your EPWM2 trips
  - Digital Compare 2 events are used for cycle-by-cycle trips

To clarify, is the above desired? Or did you want EPWM1 and EPWM2 behaving the same way when reacting to TRIPIN4 (DCAH/DCBH high)?

Best Regards,

Allison

0 JUNYEONG OH 7 months ago in reply to Allison Nguyen

Prodigy 40 points

Hi Allison

During the experiment, phase shift deactivation of EPWM1 and EPWM2 was reflected.

What I want to implement is to use trip zone 1 to output epwm1 synchronized to the input when the input waveform matches the DACHVALS.bit.dacval value of cmpss1, and to use trip zone 1 to output epwm2 synchronized to that input when the input waveform matches the DACLVALS.bit.DACVAL value of cmpss2.
If both values are hit at the same time, I want to display synchronized epwm1 and epwm2.

If it is appropriate to use a one-shot function, would it be better to link epwm2 with DCAEVT1 and DCBEVT1 instead of DCAEVT2 and DCBEVT2?

Sincerely,

Junyeong Oh

0 Allison Nguyen 7 months ago in reply to JUNYEONG OH

TI__Mastermind 20630 points

Hi Junyeong,

If you are trying to use one-shot trips, you must use DCAEVT1 and DCBEVT1 as the trips for these are inherently one-shot trips. I'm not sure I fully understand what output waveform you are trying to produce, though. Do you mind making a quick sketch or diagram of the desired EPWM output in response to the signal from the CMPSS so I can get the full picture? Are you clearing the one-shot trips as well?

Best Regards,

Allison

0 JUNYEONG OH 7 months ago in reply to Allison Nguyen

Prodigy 40 points

Hi Allison,

This figure below is a diagram of the desired EPWM output in response to the signal from the CMPSS.

When cmpss1 and cmpss2 receive a sine wave under 3.3V, we plan to implement trip zone 1 according to the reference value set by DACHVAL of CMPSS1 and DACLVAL of CMPSS2.
First, it is shown as in the third picture, but since TBCTR=0 when a trip zone occurs, the third waveform in the center may be wrong.
Ultimately, I would like to create an epwm waveform synchronized to the input waveform and output it simultaneously, like the two waveforms at the bottom.

Sincerely,

Junyeong Oh

0 Allison Nguyen 7 months ago in reply to JUNYEONG OH

TI__Mastermind 20630 points

Hi Junyeong,

Thank you for your follow up and helpful diagram. I will try to get back to you this week, but please note I am out of office the next few days.

Best Regards,

Allison

0 Allison Nguyen 7 months ago in reply to JUNYEONG OH

TI__Mastermind 20630 points

Hi Junyeong,

Thanks for the patience while I was out. I first wanted to check back in - have you made any further changes or progress on this issue? Are you still having trouble setting up the waveform?

Best Regards,

Allison