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TMS320F280039C: Interleaved CRM totem PFC EPWM configuration

Part Number: TMS320F280039C
Other Parts Discussed in Thread: TIDM-02013

Tool/software:

Hi Champ,

I am asking for my customer on implementing interleaved CRM PFC.

There are two epwm sets, epwm1 as main set, and epwm2 as interleaved set.

epwm2 has a T/2 delay with epwm1, and the inductor current waveform is shown below. 

Red waveform as epwm1, and blue waveform as epwm2.

  (Figure inductor current)

In this app. note (SPRACX0) single phase CRM PFC implementation, epwm1 time base is sync. when the CMPSS1 event occurs with DC submodule (DCAEVT1.sync), logically speaking with interleaved epwm configuration, epwm2 time base should also be sync. when the CMPSS2 event occurs with DC submodule (DCAEVT2.sync). 

To add the T/2 delay requirement on epwm2 (T/2 delay with epwm1), EPWMxSYNCI should be used here to synchronize the time-base counter with the counter of epwm1 module, right ? Is the interleaved set epwm2 supposed to be configured in such for interleaved CRM PFC ? not really sure the actually topology actives like such.

Do we have any experience to implement interleaved CRM PFC epwm configuration?

Thanks and regards,

Johnny

  • Hi Johnny,

    You can do this using ePWM phase shift. Could you please refer to TIDM-02013 code base. Please refer to below lines of code in ttplpfc_hal.c file.

    void TTPLPFC_HAL_setupPWM(uint16_t pwm_period_ticks,
    uint16_t pwm_db_ticks_red, uint16_t pwm_db_ticks_fed)
    {

    TTPLPFC_HAL_setupPWM_UpDownCountWithDeadband(TTPLPFC_LOW_FREQ_PWM_BASE, pwm_period_ticks, pwm_db_ticks_red, pwm_db_ticks_fed);
    TTPLPFC_HAL_setupPWM_UpDownCountWithDeadband(TTPLPFC_HIGH_FREQ_PWM1_BASE, pwm_period_ticks, pwm_db_ticks_red, pwm_db_ticks_fed);
    TTPLPFC_HAL_setupPWM_UpDownCountWithDeadband(TTPLPFC_HIGH_FREQ_PWM2_BASE, pwm_period_ticks, pwm_db_ticks_red, pwm_db_ticks_fed);

    HWREGH(TTPLPFC_LOW_FREQ_PWM_BASE + EPWM_O_AQCTLA) = 0;
    EPWM_setDeadBandDelayMode(TTPLPFC_LOW_FREQ_PWM_BASE, EPWM_DB_RED, false);
    EPWM_setDeadBandDelayMode(TTPLPFC_LOW_FREQ_PWM_BASE, EPWM_DB_FED, false);

    //
    // Setup phase sync
    //
    //


    EPWM_disablePhaseShiftLoad(TTPLPFC_LOW_FREQ_PWM_BASE);
    EPWM_enableSyncOutPulseSource(TTPLPFC_LOW_FREQ_PWM_BASE,
    EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);

    EPWM_enablePhaseShiftLoad(TTPLPFC_HIGH_FREQ_PWM1_BASE);
    EPWM_setSyncInPulseSource(TTPLPFC_HIGH_FREQ_PWM1_BASE, TTPLPFC_PWM_SYNC_SOURCE);
    EPWM_setPhaseShift(TTPLPFC_HIGH_FREQ_PWM1_BASE, 2 );
    EPWM_setCountModeAfterSync(TTPLPFC_HIGH_FREQ_PWM1_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);

    #if TTPLPFC_TOTAL_NO_PHASES == 2
    EPWM_enablePhaseShiftLoad(TTPLPFC_HIGH_FREQ_PWM2_BASE);
    EPWM_setSyncInPulseSource(TTPLPFC_HIGH_FREQ_PWM2_BASE, TTPLPFC_PWM_SYNC_SOURCE);
    //
    // 180 Degree Phase Shift for 2 phase interleaving
    //
    EPWM_setPhaseShift(TTPLPFC_HIGH_FREQ_PWM2_BASE,
    ((uint16_t)((float32_t)TTPLPFC_PWM_PERIOD/(float32_t)(2.0)))-2);
    EPWM_setCountModeAfterSync(TTPLPFC_HIGH_FREQ_PWM2_BASE,
    EPWM_COUNT_MODE_DOWN_AFTER_SYNC);

    #elif TTPLPFC_TOTAL_NO_PHASES == 3
    EPWM_enablePhaseShiftLoad(TTPLPFC_HIGH_FREQ_PWM2_BASE);
    EPWM_setSyncInPulseSource(TTPLPFC_HIGH_FREQ_PWM2_BASE, TTPLPFC_PWM_SYNC_SOURCE);

    EPWM_enablePhaseShiftLoad(TTPLPFC_HIGH_FREQ_PWM3_BASE);
    EPWM_setSyncInPulseSource(TTPLPFC_HIGH_FREQ_PWM3_BASE, TTPLPFC_PWM_SYNC_SOURCE);

    EPWM_setPhaseShift(TTPLPFC_HIGH_FREQ_PWM2_BASE,
    (2 + (uint16_t)((float32_t)pwm_period_ticks /
    (float32_t)(3.0))));
    EPWM_setCountModeAfterSync(TTPLPFC_HIGH_FREQ_PWM2_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);

    EPWM_setSyncOutPulseMode(TTPLPFC_HIGH_FREQ_PWM3_BASE, EPWM_SYNC_OUT_PULSE_ON_SOFTWARE);
    EPWM_setPhaseShift(TTPLPFC_HIGH_FREQ_PWM3_BASE,
    (2 + (uint16_t)((float32_t)pwm_period_ticks /
    (float32_t)(3.0))));
    EPWM_setCountModeAfterSync(TTPLPFC_HIGH_FREQ_PWM3_BASE, EPWM_COUNT_MODE_DOWN_AFTER_SYNC);

    #endif

    Thanks

    Srikanth