TMS320F280039C: some questions about MCU power

Angela,

I would refer to this section of the datasheet to give some needed background for the sections mentioned above:

https://www.ti.com/document-viewer/TMS320F280039/datasheet#GUID-E311B1CE-8214-4C20-840B-DAF9E1F06EA8/GUID-3EC1BB52-69E9-4835-8374-8B9FD25AEFE4

The assumption here is that VDD is monitored externally, so the goodness of VDD is not in question for the external VDD supply case.

So for 2.1 there is no requirement, with the assumption that VDD is being monitored.  Else, the internal VDD POR trip point is too low to guarantee correct device operation until it is trigger and drives the XRSn low

For 2.2:

The risk on power up is if the rise time is too slow, then the BOR could release before the voltage has settled in the correct region.  Customer can refer to the timing delays along with the range for BOR release to determine if there is risk or not

For power down I think same risk of being too slow, although it should be less risk than power up since BOR is fully functional.

In both cases I think if there is too fast of a ramp there is risk of activating the ESD diodes in the device, and drawing excess current and/or latching up the IO buffer.

For ramp rate on VDD, since again we have assumption there is external supervisor on this rail, it is more about a controlled power up seen by the device.

Best,

Matthew

1. In conclusion:

1.1  Power-up/down timing of 3.3V and 1.2V is not a problem;

1.2  When Power-up/down ,slew rate of 3.3V and 1.2V  is a risk.  is it right?

2. Solution:

This is correct, can you give some the IC part numbers, just so I can take a look to see how far off we are from our spec?  We may have to use LDO based supply vs buck if this is more an issue with that topology.

Best,

Matthew

2. I haven't found a buck IC without soft start function yet.

Dang,

Can you comment which of the below startup graphs from the TPS562201 matches how you have implemented in the system?  Also, since these just show 1V for Vout; can you comment on what you see when configured for 3.3V Vout?  Is the power up time 3x shown below, or still 1ms?

Best,
Matthew

1. I'm referring to the time at the arrow (TPS562201)

2. The following is our measured waveform( CH1:3.3V)  has a relatively large delay time about 1 ms.

Dang,

Thanks for the new info, this helps alot. 

I think the VDD hold off is helping us here, to avoid an issue with the slower rise time of the VDDIO line. 

Since the VDD is not coming on at all until ~2.85V it is also holding off XRSn during what might otherwise be an indeterminant time.  When it does come up, VDDIO is already within good range, such that the internal BOR monitor is stable/known good at this point as well.

You can also see the XRSn line is not releasing until the expected range we have in the DS, which would also be an indication that things are not settled internally.

If we believe that this relationship of VDDIO/VDD will hold I'm OK with the violation of the min slew rate, the device will come out of reset cleanly and operate correctly.

Just curious, what is the source for VDD that holds off until VDDIO is almost done with its ramp?  

Best,
Matthew

I don't know what you're talking about。

1. VDD is 1.2V, not 3.3V;

2. VDDIO (3.3V)→LDO→ VDD (1.2V) 

I understand the  normal Power Up Sequence(Figure 6-3)，but not solve my  current problems (eg. the waveforms that I display)

“ However, based on your waveform, since VDD(1.2V) does not come active until VDDIO(3.3V) is at or near the 2.60V this is mitigating the slow ramp rate on VDDIO, holding off reset de-assertion correctly “

why 2.6V is an  appropriate value ?

???

Dang,

The 2.45V is not in the DS, by specifying the ramp rates of the VDDIO/VDD and how the internal POR/BOR is constructed we will make sure that the BOR is accurately monitoring the VDDIO rail before releasing XRSn.

However, in your case, since VDD is held low and does not ramp with VDDIO we don't have to be as stringent on the ramp rate, as VDD being 0V will also guarantee that XRSn is held, even if VDDIO were in specification. 

This was not a scenario we anticipated, which is why we only give ramp rates vs all the different turn on/working conditions of the different monitors inside the device.

The ramp rates, coupled with the delays in the block diagram I posted earlier, will make sure the POR/BOR is not releasing reset too soon.

Best,

Matthew

1. Test data

2. Waveform

CH1:3.3V CH3:1.2V CH2:RST

@MatthewPate ???