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Tool/software:
Hello. I am implementing BiSS-C communication using CLB.
I set it to transform the state using FSM.
Below is a logic table.
I created a logical formula based on the logic table and entered values.
And the simulation results
According to the table,
when S1/S0/E1/E0 is 0110, the next state is 10.
When S1/S0/E1/E0 is 1000, the next state should be 10.
However, the state changes to 00.
Referring to the third term of the S1n+1 expression, there is s1 & !s1.
S1n+1 should be fixed to 1.
The expression of state1 is evaluated as 0x6A48.
Any thoughts or known bugs about this?
이에 대해서 의견이나 알려진 버그가 있을까요?
Hi Seahan,
Are you able to extend the pulse width of when e1/e0 is 10? It's possible this is a timing issue where the input needs to be 10 for longer than a single FSM clock.The issue may be specific to the simulator and not the actual CLB.
Thank you,
Luke
The above table is solved with a formula.
When optimizing a logical equation with a Karnaugh map, you should not group them so that they overlap.
However, I don't know if there is an error in the calculation of the state equation going into the FSM LUT register or if it is a simulation problem.
Hi Seahan,
When you program the device with your configuration, what is the value of this register?
Thank you,
Luke
It doesn't work as the logic table says.
S1 : 0x64A8
S0 : 0x479A
It works as a logic table.
S1 : 0x64EC
S0 : 0x579B
Hi Seahan,
If you send me your .syscfg file it will be easier for me to recreate the issue on my side and determine the root cause.
Thank you,
Luke