Dear Texas Instruments Support Team,
I'm currently working on implementing SCI bootloader using example F2837xS_SCI_Flash_kernel from C2000ware.
Issue - While trying to upload code using command in terminal. After "adjusting port settings" in terminal the process is not proceeding further which provides me a options for selecting DFU(Device Firmware Update).
Hardware Setup:
- Custom PCB with TMS320F28379S.
- RS232 Out from the TMS320F28379S is connected to an RS232-to-USB converter,
which is then connected to the PC via a USB port.
Steps Followed:
1. Uploaded SCI Flash Kernel:
- I uploaded the F2837xS_SCI_Flash_kernel code to the micro controller using the XDS110 Debugger.
2. Prepared Application Code:
- I prepared an application code for a simple LED blink.
- Converted the application code to .txt format using `hex2000` via the command line.
3. Ran the Serial Flash Programmer Command:
serial_flash_programmer_appln.exe -d f2837xS -k F2837xS_sci_flash_kernel.txt -a LED_blink.txt -b 115200 -p COM9
Terminal Output:
getting comm state
building comm DCB
adjusting port settings
After this, the process doesn't proceed further. Which gives me an option to select DFU.
Things I’ve Tried So Far:
1. Checked the COM Port:
- Verified that the RS232-to-USB converter is correctly connected and recognized as COM9 in Device Manager.
2. Checked Boot Mode of the Micro controller:
- Confirmed the GPIO pins for SCI Boot Mode are configured correctly.
- Could anyone suggest what might be causing this issue?
- What further steps can I take to troubleshoot and resolve this issue?
Thanks in advance for any assistance!
Hi,
Some suggestions:
- If you wish to use SCI boot mode with standalone load of the kernel, you should use the serial_flash_programmer.exe
- Check that your GPIOs are set appropriately for SCI communication
- What GPIOs are the kernel communicating with?
Thanks,
Charles
Hi Charles,
SCI Boot Mode & Serial Flash Programmer
I’ve tried using the "serial_flash_programmer.exe"
as you suggested, but the issue remains the same. Additionally, I also experimented with a reduced baud rate, but that didn’t resolve the problem either.
GPIOs for Boot mode
The boot mode is set to SCI, with GPIO 72 set to 0 and GPIO 84 set to 1 for SCI communication.
SCI Communication pins
I’ve verified both the code and hardware for the SCI pins (GPIO 28 and 29), and everything seems to be in order. I also confirmed that SCI communication works when tested with terminal software.
Kindly suggest how can i proceed further.
Thanks
Hi,
This is likely due to a GPIO mismatch. GPIO 28 and 29 are used for the alternate GPIO pins, with GPIO 84 and 85 as defaults. Is it possible for you to:
1) Set the device in EMU boot mode for GPIO 28 and 29
2) Run the CPU1 target in CCS and then use the "serial_flash_programmer.exe" along with the arguments used:
serial_flash_programmer.exe -d f2837xS -k F2837xS_sci_flash_kernel.txt -a LED_blink.txt -b 115200 -p COM9
If you wish to use GPIO 84/85 which is being used by this mode, then you have to edit the flash kernel for these GPIO selections in project's source files.
Thanks,
Charles
Hi,
Kindly explain about the GPIO missmatch.
1.In hardware I've connected GPIO pin 72 and 84 as shown in datasheet for SCI mode.For 1 i've connected to 3.3v and for 0 I connected to gnd.
2.In example code i've selected pin 28 and 29 as shown below since pin 84 belongs to Boot mode control pin
3.As per datasheet GPIO pin 72 and 84 are boot control pins. How come can I set EMU boot mode for GPIO 28 and 29.
Hi,
The device boot ROM by default uses GPIO 84 and 85 for SCI communication.
You can set the EMU boot mode for GPIO 28 and 29 as well. Can you try loading with the EMU boot mode set for GPIO 28 and 29, the Boot Mode Select pins need not be considered since the device would be connected through JTAG in CCS.
Thanks and regards,
Charles
Hi Charles,
I tried the steps you suggested but am still facing some issues:
Could you please confirm is my procedure right? and if ok kindly suggest how to proceed.
Thanks!
What was your reduced or current baudrate?
I should add that to enter the emulation boot mode for this device, it is explained in section 7.3.2 of the Serial Flash Programming of C2000 Microcontrollers application note.
0xD00 location should contain the value 0x815A in the Memory browser.
Z1_BOOTCTRL values can only be modified by programming the OTP through the Flash API, and is not necessary is you wish to succeed doing emulation mode only at first.
Hi,
I followed the steps mentioned below but am facing an issue at the end:
1.I went to debug mode from the SCI_Flash_kernel example code in Code Composer Studio.
2.I paused the operation and opened the memory browser.
3.In the memory browser, I searched for 0x1D00 and updated the first element to 0x815A.
4.I then did RUN -> CPU Reset.
5.I pressed the Play button.
6.I ran the command from the command prompt.
"serial_flash_programmer.exe -d f2837xS -k F2837xS_sci_flash_kernel.txt -a LED_Blink.txt -b 115200 -p COM9"
7.The flash kernel got dumped.
8.I selected option 1 for DFU.
9.The application code got dumped and asked for next step ,I selected option 6 to run.
10.It then asked for the address to branch to.
11.I copied the entry point address from above and pasted it below.
12.The process gets stuck at “calling f021_SendPacket.”
How can I solve this issue?
I also tried this method by setting the SCI boot mode using the GPIO pins, but it didn't work either. Kindly suggest how can I proceed further.
Could you load the symbols for the kernel when it is running through CCS? This way we can see closer what happens with the SendPacket function.
Hi Charles,
Even though the process gets stuck at “calling f021_SendPacket”, I was able to verify that my application code was successfully uploaded to Flash via SCI by resetting the controller.
However, my main concern is that when using SCI boot mode without Emulation Boot Mode, the process does not proceed beyond the first transmission.
When running the following command in the terminal:
"serial_flash_programmer.exe -d f2837xS -k F2837xS_sci_flash_kernel.txt -a ups-gpio.txt -b 9600 -p COM9"
The process stops at:
"calling f021_DownloadKernel CPU1 Kernel
Downloading F2837xS_sci_flash_kernel.txt to device...
aa "
It does not continue further.
Could you help me resolve this issue?
Rajamurugan,
Please see section table 4-24 of the TMS320F2837xS Real-Time Microcontrollers Technical Reference Manual (Rev. I). The default GPIOs for TX/RX are 84 and 85 in boot ROM.
When you load the kernel through GPIOs 28+29 using emulation boot, you manually override this setting by modifying the value stored at 0xD00. This is not persistent through a power reset. To change it permanently, you must set the OTP BMODE value to 0x81 as listed in the table.
An alternative option is to use GPIOs 84 and 85.
Best,
Alex
Hi Alex,
I am facing an issue regarding SCI boot mode when using alternate pins.
Issue: When using SCI boot mode with alternate pins (after modifying the example code), the process does not proceed beyond the first transmission—it gets stuck at that point.
Steps I Followed:
1.Modified the example code "F2837xS_SCI_FLASH_KERNEL" from C2000Ware to work with alternate pins as shown below:
In F2837xS_sci_flash_kernel.c, I updated the code to:
"EntryAddr = SCI_GetFunction(SCI_BOOT_ALTERNATE);"
2.Uploaded the code using CCS (I didn't performed any power reset after this).
3.Connected the SCI pins of the MCU to the PC.
4.Ran the following command:
"serial_flash_programmer.exe -d f2837xS -k F2837xS_sci_flash_kernel.txt -a ups-gpio.txt -b 9600 -p COM9"
5.However, the process did not proceed beyond the first transmission
"calling f021_DownloadKernel CPU1 Kernel
Downloading F2837xS_sci_flash_kernel.txt to device...
aa"
1.Do I need to set OTP BMODE value if yes how to set that value.
2.Another concern is if I need to use the default 84 and 85 pin as you suggested How come I change the default boot mode selection pin which is 84 and 72 to some other value. For example how do I change the Boot mode selection pin from 72 and 84 to 3 and 2.
My ultimate thing is to 1st set the Boot selection pin to sci mode and upload firmware then set the Boot selection pin to flash mode to always boot from flash when firmware update is needed I can physically change them to sci mode .
Kindly help me to resolve this issue
Rajamurugan,
You can change either the boot mode select pins or the SCI pins so that they don't conflict, both require programming OTP. This can be done using the Flash API. To change and/or configure the boot select pins, refer to TMS320F2837xS Real-Time Microcontrollers Technical Reference Manual (Rev. I) section 4.5, and to change the SCI pins see section 4.10.6.
As for your current issue, this occurs even when using emulation boot correct? Can you confirm the kernel is running on the device? After loading through CCS, can you pause the program and check if it is in autobaud?
Best,
Alex
Hi Alex,
No, while working with emulation boot mode, everything works well until the last step. When I select the DFU option, the application code gets loaded, and I am prompted for the next step. I select option 6 to run.
It then asks for the address to branch to. I copy the entry point address from above and paste it as required.
At this point, the process gets stuck at "calling f021_SendPacket."
Even though the process doesn't complete, when I reset the MCU, it successfully boots from flash and runs the application code. So, this issue only occurs when I dump the code using the XDS110 debugger and follow the steps mentioned previously(Modifying code as mentioned above)
Kindly help me to solve why it is not going beyond first transmission.
I also have another question: :- Mean time I've decided to use GPIO 3 and 2 for Boot mode select pin instead of 72 and 84 to avoid conflict during SCI operation.
Is there any detailed example code or application note available for changing the boot mode select pins by programming the OTP?
Rajamurugan,
Can you enable verbose mode by adding the "-v" option when calling the host programmer?
Best,
Alex
Hi Alex,
Yes I can enable verbose mode by adding "-v" at end. I have attached image of the result
During my 1st attempt it stuck at 1st transmission and during my second attempt there was an error with autobaud lock echo back.
And Kindly share If there is any detailed example code or application note available for changing the boot mode select pins by programming the OTP?
Rajamurugan,
There are not any example projects for programming the boot mode select pins, the best reference would be the flash programming examples, which you can modify to write the to the desired OTP ranges. The TMS320F2837xS Flash API Reference Guide (Rev. A) will also be helpful in doing this.
I am still working on replicating this and will hopefully have a more in-depth response tomorrow or early next week.
I would also like to ensure that I am understanding correctly, and that you are seeing two separate issues:
Best,
Alex
Hi Alex,
When using emulation boot (no power reset, load the kernel through CCS), the kernel hangs on calling f021_SendPacket
Your understanding of this issue is correct.
But,
For this
When booting from SCI (after power reset), the device fails to autobaud when uploading the kernel and afterwards hangs. The point at which it fails is not consistent
I did boot from sci but before that I uploaded the modified code using ccs to assign alternate pins for sci.
I used below mentioned steps
1.Modified the example code "F2837xS_SCI_FLASH_KERNEL" from C2000Ware to work with alternate pins as shown below:
In F2837xS_sci_flash_kernel.c, I updated the code to:
"EntryAddr = SCI_GetFunction(SCI_BOOT_ALTERNATE);"
2.Uploaded the code using CCS (I didn't performed any power reset after this).
3.Connected the SCI pins of the MCU to the PC.
4.Ran the following command:"serial_flash_programmer.exe -d f2837xS -k F2837xS_sci_flash_kernel.txt -a ups-gpio.txt -b 9600 -p COM9"
5.However, the process did not proceed beyond the first transmission
"calling f021_DownloadKernel CPU1 Kernel
Downloading F2837xS_sci_flash_kernel.txt to device...
aa"
Hope this helps and I appreciate the assistance here Thanks!
Rajamurugan,
For the second issue (the autobaud one), try using serial_flash_programmer_appln.exe. This version only sends the app over SCI, as the kernel has already been placed in RAM by CCS.
I am still looking into the first issue.
Best,
Alex
Hi Alex,
Could you kindly help me with this?
I tried the steps you mentioned, and the application successfully loads to Flash. However, the kernel hangs at f021_SendPacket, which is the same issue observed in emulation mode.
I am currently working on implementing the Flash API to change the Boot Mode Select Pins.
BMSP0: Changing from GPIO 84 to GPIO 73
This will allow me to use the default SCI boot mode pins (GPIO 84, GPIO 85) for firmware updates.
Final Requirement:
Under normal operation, the MCU should always boot from Flash.
When a firmware update is needed, I will set the Boot Mode Select Pins to SCI mode, update the firmware, and then set them back to Flash mode.
After a power reset, the MCU should always boot from Flash unless manually set to SCI mode for an update.
Major Concern:
As per my understanding, if I correctly configure the Boot Mode Select Pins , I should be able to successfully load the kernel and application code using serial_flash_programmer.exe.
without the need of using JTAG and CCS?
Could you please confirm if my approach is correct?
Rajamurugan,
Yes, if the GPIOs and boot mode are properly configured and selected, you will be able to load both the kernel and application code over SCI.
Can you try lowering the baud rate under 100K?
If that doesn't work, can you load the kernel through CCS and go through the normal loading process up until f021_SendPacket, then pause the kernel in CCS. Where is it getting stuck?
Best,
Alex
Hi Alex,
Yes, if the GPIOs and boot mode are properly configured and selected, you will be able to load both the kernel and application code over SCI.
I need modify"BMSP0: Changing from GPIO 84 to GPIO 73" but before modification(writing to OTP) is there any ways to check its working in emulation boot mode.
If yes suggest how to do.
Can you try lowering the baud rate under 100K?
I tired with baud rate 9600,19200 results are same no improvements in error
If that doesn't work, can you load the kernel through CCS and go through the normal loading process up until f021_SendPacket, then pause the kernel in CCS. Where is it getting stuck?
Then as suggested I've uploaded the kernel code using CCS in debug mode to play and pause code
The I ran the below mentioned command
"serial_flash_programmer_appln.exe -d f2837xS -k F2837xS_sci_flash_kernel.txt -a ups-gpio.txt -p COM8 -b 19200 -v"
When the process hangs at f021_SendPacket I paused the code and the result I've attached in below image
Kindly do the needful
Rajamurugan,
To test your OTP configuration, see section 4.5 and table 4-6 of the TMS320F2837xS Real-Time Microcontrollers Technical Reference Manual (Rev. I). In addition to emulating the boot mode, you can also test boot mode select pin changes.
After f021_SendPacket, can you try sending a second run command (type 6, then Enter)? If that doesn't do anything, can you show the contents of the SCI TX and RX buffers (can be found in the registers view).
Best,
Alex
Hi Alex,
Sorry for the delayed response
Below is the screenshot of the contents of SCI TX and RX buffer as requested.
Rajamurugan,
I was finally able to recreate this issue today and will try and find a solution soon. In the meantime, could you share a picture of your call stack?
Best,
Alex
Hey Rajamurugan,
Can you try inserting a no-op at the bottom of the while loop in the function SCI_GetFunction in SCI_GetFunction.c?
The resulting code snippet will look like:
// // Send the packet and if NAK send again. // while(SCI_SendPacket(command, statusCode.status, 12, (Uint16*)&statusCode.address, statusCode.flashAPIError, (Uint16*)&statusCode.flashAPIFsmStatus)) // // Get next Packet // __asm(" NOP"); command = SCI_GetPacket(&length, data); //get next packet
Best,
Alex
Hi Alex,
I tried what you have suggested output found to be satisfied. Below I've attached my output.
However I'm facing some issue while using my real application code above steps were done using a simple led blink code.
Here I've attached my screenshot for your reference.
Kindly help me out on how to proceed.
Rajamurugan,
Could you confirm whether or not the sections (mapped to the flash) in the linker command file are aligned using ALIGN(8)? If not, can you please align them?
Best,
Alex
Hi Alex,
Below are the modifications I made in code correct me if I'm wrong
//28379S_FLASH_lnk.cmd //Line numbers mentioned below 0: .cinit : > FLASHB PAGE = 0, ALIGN(8) 81: .pinit : > FLASHB, PAGE = 0, ALIGN(8) 82: .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8) 83: codestart : > BEGIN PAGE = 0, ALIGN(8) 95: PAGE = 0, ALIGN(8) 105: PAGE = 0, ALIGN(8) 115: .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8) 116: .switch : > FLASHB PAGE = 0, ALIGN(8)
Output is not as expected the application code is not loaded in flash.
process hangs as shown below
Rajamurugan,
That linker file looks good. Are you passing the .out or the .txt image to the host programmer as your application? The host programmer and kernel expect the application to be in a certain ASCII format which must be generated using a post-build step. More information on this can be found in Serial Flash Programming of C2000 Microcontrollers (Rev. H) section 3.
Best,
Alex
Hi Alex,
By mistake I used .out file instead of .txt file.
Now it works good.
I need another help regarding programming OTP memory
I tried EMU boot mode to test change in BMSP
I tried using 0xFE5A for 0xD00 and 0x004A for 0xD01 but it is not working.
My requirement is to set BMODE to SCI and BMSP0 to 73
Rajamurugan,
Apologies, I was mistaken earlier, and emulation of the boot mode select pins is not available on this device, you will have to program the OTP region.
The BOOTCTRL register is located at address 0x7801E and should be programmed with the following words: 0x5A0B 0x4948 0xFE5A 0x0049. This will set BMSP0 = GPIO73, BMSP1 = GPIO72, and the default boot mode as read the boot mode select pins.
Please note that the Flash API has a 64-bit minimum when programming in order to properly compute the ECC value, so your buffer might need to include some of the surrounding memory.
Best,
Alex
HI Alex,
Can you try inserting a no-op at the bottom of the while loop in the function SCI_GetFunction in SCI_GetFunction.c?
Even though the command ends without any hang ,but code is not running from flash after this step
Kindly help me on this
Rajamurugan,
Does the LED blinky example also fail to run after the command ends?
Also, I saw your earlier response (not sure where it went) and you are correct -- there are registers for emulating the boot mode select pins.
Try using 0xD00 = 0xFE5A, 0xD01 = 0x0049.
Best,
Alex
Hi Alex,
Yes The LED Blinky example also fails to run.
I have successfully emulated the BMSP by using value FE5A and 004A , but my doubt are
1.What value I need to write to Z1_BOOTCTRL in OTP using on chip menu in debug.
As per result from EMU boot mode the value is 0x004A 0B5A
But I noticed the default was 0xFFFFFFFF so as per this I assume the value would be 0xFF4A 0B5A
Kindly let me know the correct value, so that I can try programming the OTP memory
Kindly Let me know the solution for why it is failing to run and the correct value for register.
Hi Rajamurugan,
I see you have two on-going threads discussing the same topics. I'm going to close the other thread and address your questions on this thread.
But I noticed the default was 0xFFFFFFFF so as per this I assume the value would be 0xFF4A 0B5A
That is not correct. Since you require BMSP0 = GPIO73 and BMSP1 = GPIO72, then you want to keep the BOOTCTRL configuration as 0x004A 0B5A. The '00' will keep BMSP1 in its default configuration (GPIO72), but 'FF' will set it to GPIO255.
Try using 0xD00 = 0xFE5A, 0xD01 = 0x0049
This configuration will have the device read the emulation BMSPs, but use the boot mode (if programmed) in the OTP BOOTCTRL register when GET mode is picked.
1.What value I need to write to Z1_BOOTCTRL in OTP using on chip menu in debug.
You will need to program 0x004A 0B5A into Z1-BOOTCTRL to configure BMSP0=GPIO73, BMSP1=GPIO72, and BMODE=Boot to Flash. You can then boot the device to Flash by enabling GET mode (setting BMSP0 and BMSP1 both to 1).
Best,
Matt
Hi Matt,
Thanks for the response!
I successfully used 0x004A 0B5A it's working good as expected.
Does the LED blinky example also fail to run after the command ends?
But this issue still persist Kindly provide solution for this issue.
Hi Rajamurugan,
Looking at your application's linker command file, it seems like you're placing it in FlashB ie. 0x082000. However, the Flash boot (0x0B) entry point address is 0x80000. For the device to successfully boot to your application, then you need to put the application at the Flash entry point 0x80000.
Best,
Matt
Hi Matt,
/*Exsisting*/ /* Flash sectors */ FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ /* Allocate program areas: */ .cinit : > FLASHB PAGE = 0, ALIGN(8) .pinit : > FLASHB, PAGE = 0, ALIGN(8) .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8) codestart : > BEGIN PAGE = 0, ALIGN(8) /* Initalized sections go in Flash */ .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8) .switch : > FLASHB PAGE = 0, ALIGN(8) /*Modified*/ .cinit : > FLASHA PAGE = 0, ALIGN(8) .pinit : > FLASHA, PAGE = 0, ALIGN(8) .text : >> FLASHA | FLASHB | FLASHC | FLASHD PAGE = 0, ALIGN(8) codestart : > BEGIN PAGE = 0, ALIGN(8) .switch : > FLASHA PAGE = 0, ALIGN(8)
Here I have attached my existing and modified piece of code.
Is this correct ? or do I need to make some other changes.
I tried this and its not working as required.
1.Kindly provide some detailed insights and steps.
2.And for the info I haven't made any changes to linker file so by default it goes to FLASH B right? so in future I need to make all these changes to make SCI bootloader work or is there is anything I can do while configuring initially.
Hi,
Did you also modify the codestart (BEGIN) to 0x80000? If so, please send me your .map file for the build so I can see where the application is being loaded.
2.And for the info I haven't made any changes to linker file so by default it goes to FLASH B right? so in future I need to make all these changes to make SCI bootloader work or is there is anything I can do while configuring initially.
Can you re-clarify this? I'm not sure I understand completely.
Best,
Matt
Hi matt,
Can you re-clarify this? I'm not sure I understand completely
I haven't changed the linker file, so by default, the code is placed in FLASH B, right?
In the future, do I always need to modify the linker file for the SCI bootloader to work, or is there a way to configure it correctly from the start?
Did you also modify the codestart (BEGIN) to 0x80000? If so, please send me your .map file for the build so I can see where the application is being loaded.
Yes the codestart (BEGIN) was set to 0x80000
****************************************************************************** TMS320C2000 Linker PC v22.6.1 ****************************************************************************** >> Linked Thu Mar 27 09:02:30 2025 OUTPUT FILE NAME: <ups-gpio.out> ENTRY POINT SYMBOL: "_c_int00" address: 00082c99 MEMORY CONFIGURATION name origin length used unused attr fill ---------------------- -------- --------- -------- -------- ---- -------- PAGE 0: RAMM0 00000122 000002de 00000000 000002de RWIX RAMLS0 00008000 00000800 00000072 0000078e RWIX RAMLS1 00008800 00000800 00000000 00000800 RWIX RAMLS2 00009000 00000800 00000000 00000800 RWIX RAMLS3 00009800 00000800 00000000 00000800 RWIX RAMLS4 0000a000 00000800 00000000 00000800 RWIX RAMD0 0000b000 00000800 00000000 00000800 RWIX RAMGS14 0001a000 00001000 00000000 00001000 RWIX RAMGS15 0001b000 00001000 00000000 00001000 RWIX BEGIN 00080000 00000002 00000002 00000000 RWIX FLASHA 00080002 00001ffe 00000084 00001f7a RWIX FLASHB 00082000 00002000 00000dd5 0000122b RWIX FLASHC 00084000 00002000 00000000 00002000 RWIX FLASHD 00086000 00002000 00000072 00001f8e RWIX FLASHE 00088000 00008000 00000000 00008000 RWIX FLASHF 00090000 00008000 000001c0 00007e40 RWIX FLASHG 00098000 00008000 00000000 00008000 RWIX FLASHH 000a0000 00008000 00000000 00008000 RWIX FLASHI 000a8000 00008000 00000000 00008000 RWIX FLASHJ 000b0000 00008000 00000000 00008000 RWIX FLASHK 000b8000 00002000 00000000 00002000 RWIX FLASHL 000ba000 00002000 00000000 00002000 RWIX FLASHM 000bc000 00002000 00000000 00002000 RWIX FLASHN 000be000 00002000 00000000 00002000 RWIX FLASHO 000c0000 00002000 00000000 00002000 RWIX FLASHP 000c2000 00002000 00000000 00002000 RWIX FLASHQ 000c4000 00002000 00000000 00002000 RWIX FLASHR 000c6000 00002000 00000000 00002000 RWIX FLASHS 000c8000 00008000 00000000 00008000 RWIX FLASHT 000d0000 00008000 00000000 00008000 RWIX FLASHU 000d8000 00008000 00000000 00008000 RWIX FLASHV 000e0000 00008000 00000000 00008000 RWIX FLASHW 000e8000 00008000 00000000 00008000 RWIX FLASHX 000f0000 00008000 00000000 00008000 RWIX FLASHY 000f8000 00002000 00000000 00002000 RWIX FLASHZ 000fa000 00002000 00000000 00002000 RWIX FLASHAA 000fc000 00002000 00000000 00002000 RWIX FLASHAB 000fe000 00002000 00000000 00002000 RWIX RESET 003fffc0 00000002 00000000 00000002 RWIX PAGE 1: BOOT_RSVD 00000002 00000120 00000000 00000120 RWIX RAMM1 00000400 00000400 00000100 00000300 RWIX ADCA_RESULT 00000b00 00000020 00000018 00000008 RWIX ADCB_RESULT 00000b20 00000020 00000018 00000008 RWIX ADCC_RESULT 00000b40 00000020 00000018 00000008 RWIX ADCD_RESULT 00000b60 00000020 00000018 00000008 RWIX CPU_TIMER0 00000c00 00000008 00000008 00000000 RWIX CPU_TIMER1 00000c08 00000008 00000008 00000000 RWIX CPU_TIMER2 00000c10 00000008 00000008 00000000 RWIX PIE_CTRL 00000ce0 00000020 0000001a 00000006 RWIX PIE_VECT 00000d00 00000200 000001c0 00000040 RWIX DMA 00001000 00000200 000000e0 00000120 RWIX CLA1 00001400 00000040 0000003e 00000002 RWIX EPWM1 00004000 00000100 00000100 00000000 RWIX EPWM2 00004100 00000100 00000100 00000000 RWIX EPWM3 00004200 00000100 00000100 00000000 RWIX EPWM4 00004300 00000100 00000100 00000000 RWIX EPWM5 00004400 00000100 00000100 00000000 RWIX EPWM6 00004500 00000100 00000100 00000000 RWIX EPWM7 00004600 00000100 00000100 00000000 RWIX EPWM8 00004700 00000100 00000100 00000000 RWIX EPWM9 00004800 00000100 00000100 00000000 RWIX EPWM10 00004900 00000100 00000100 00000000 RWIX EPWM11 00004a00 00000100 00000100 00000000 RWIX EPWM12 00004b00 00000100 00000100 00000000 RWIX ECAP1 00005000 00000020 00000020 00000000 RWIX ECAP2 00005020 00000020 00000020 00000000 RWIX ECAP3 00005040 00000020 00000020 00000000 RWIX ECAP4 00005060 00000020 00000020 00000000 RWIX ECAP5 00005080 00000020 00000020 00000000 RWIX ECAP6 000050a0 00000020 00000020 00000000 RWIX EQEP1 00005100 00000040 00000022 0000001e RWIX EQEP2 00005140 00000040 00000022 0000001e RWIX EQEP3 00005180 00000040 00000022 0000001e RWIX DACA 00005c00 00000010 00000008 00000008 RWIX DACB 00005c10 00000010 00000008 00000008 RWIX DACC 00005c20 00000010 00000008 00000008 RWIX CMPSS1 00005c80 00000020 00000020 00000000 RWIX CMPSS2 00005ca0 00000020 00000020 00000000 RWIX CMPSS3 00005cc0 00000020 00000020 00000000 RWIX CMPSS4 00005ce0 00000020 00000020 00000000 RWIX CMPSS5 00005d00 00000020 00000020 00000000 RWIX CMPSS6 00005d20 00000020 00000020 00000000 RWIX CMPSS7 00005d40 00000020 00000020 00000000 RWIX CMPSS8 00005d60 00000020 00000020 00000000 RWIX SDFM1 00005e00 00000080 00000080 00000000 RWIX SDFM2 00005e80 00000080 00000080 00000000 RWIX MCBSPA 00006000 00000040 00000024 0000001c RWIX MCBSPB 00006040 00000040 00000024 0000001c RWIX SPIA 00006100 00000010 00000010 00000000 RWIX SPIB 00006110 00000010 00000010 00000000 RWIX SPIC 00006120 00000010 00000010 00000000 RWIX SPID 00006130 00000010 00000000 00000010 RWIX UPP 00006200 00000100 00000048 000000b8 RWIX WD 00007000 00000040 0000002b 00000015 RWIX NMIINTRUPT 00007060 00000010 00000007 00000009 RWIX XINT 00007070 00000010 0000000b 00000005 RWIX SCIA 00007200 00000010 00000010 00000000 RWIX SCIB 00007210 00000010 00000010 00000000 RWIX SCIC 00007220 00000010 00000010 00000000 RWIX SCID 00007230 00000010 00000010 00000000 RWIX I2CA 00007300 00000040 00000022 0000001e RWIX I2CB 00007340 00000040 00000022 0000001e RWIX ADCA 00007400 00000080 00000080 00000000 RWIX ADCB 00007480 00000080 00000080 00000000 RWIX ADCC 00007500 00000080 00000080 00000000 RWIX ADCD 00007580 00000080 00000080 00000000 RWIX INPUT_XBAR 00007900 00000020 00000020 00000000 RWIX XBAR 00007920 00000020 00000020 00000000 RWIX SYNC_SOC 00007940 00000010 00000006 0000000a RWIX DMACLASRCSEL 00007980 00000040 0000001a 00000026 RWIX EPWM_XBAR 00007a00 00000040 00000040 00000000 RWIX CLB_XBAR 00007a40 00000040 00000000 00000040 RWIX OUTPUT_XBAR 00007a80 00000040 00000040 00000000 RWIX GPIOCTRL 00007c00 00000180 00000180 00000000 RWIX GPIODAT 00007f00 00000030 00000030 00000000 RWIX RAMLS5 0000a800 00000800 00000074 0000078c RWIX RAMD1 0000b800 00000800 00000000 00000800 RWIX RAMGS0 0000c000 00001000 00000000 00001000 RWIX RAMGS1 0000d000 00001000 00000000 00001000 RWIX RAMGS2 0000e000 00001000 00000000 00001000 RWIX RAMGS3 0000f000 00001000 00000000 00001000 RWIX RAMGS4 00010000 00001000 00000000 00001000 RWIX RAMGS5 00011000 00001000 00000000 00001000 RWIX RAMGS6 00012000 00001000 00000000 00001000 RWIX RAMGS7 00013000 00001000 00000000 00001000 RWIX RAMGS8 00014000 00001000 00000000 00001000 RWIX RAMGS9 00015000 00001000 00000000 00001000 RWIX RAMGS10 00016000 00001000 00000000 00001000 RWIX RAMGS11 00017000 00001000 00000000 00001000 RWIX RAMGS12 00018000 00001000 00000000 00001000 RWIX RAMGS13 00019000 00001000 00000000 00001000 RWIX EMIF1 00047000 00000800 00000070 00000790 RWIX EMIF2 00047800 00000800 00000070 00000790 RWIX CANA 00048000 00000800 00000164 0000069c RWIX CANB 0004a000 00000800 00000164 0000069c RWIX FLASHPUMPSEMAPHORE 00050024 00000002 00000002 00000000 RWIX DEV_CFG 0005d000 00000180 0000012e 00000052 RWIX ANALOG_SUBSYS 0005d180 00000080 00000048 00000038 RWIX CLK_CFG 0005d200 00000100 00000032 000000ce RWIX CPU_SYS 0005d300 00000100 00000082 0000007e RWIX ROMPREFETCH 0005e608 00000002 00000002 00000000 RWIX DCSM_Z1 0005f000 00000030 00000024 0000000c RWIX DCSM_Z2 0005f040 00000030 00000024 0000000c RWIX DCSM_COMMON 0005f070 00000010 00000008 00000008 RWIX MEMCFG 0005f400 00000080 00000080 00000000 RWIX EMIF1CONFIG 0005f480 00000020 00000020 00000000 RWIX EMIF2CONFIG 0005f4a0 00000020 00000020 00000000 RWIX ACCESSPROTECTION 0005f4c0 00000040 00000040 00000000 RWIX MEMORYERROR 0005f500 00000040 00000040 00000000 RWIX ROMWAITSTATE 0005f540 00000002 00000002 00000000 RWIX FLASH0_CTRL 0005f800 00000300 00000182 0000017e RWIX FLASH0_ECC 0005fb00 00000040 00000028 00000018 RWIX FLASH1_CTRL 0005fc00 00000300 00000182 0000017e RWIX FLASH1_ECC 0005ff00 00000040 00000028 00000018 RWIX DCSM_Z1_OTP 00078000 00000020 00000020 00000000 RWIX DCSM_Z2_OTP 00078200 00000020 00000020 00000000 RWIX SECTION ALLOCATION MAP output attributes/ section page origin length input sections -------- ---- ---------- ---------- ---------------- .cinit 0 00080008 00000084 00080008 0000001d F2837xS_struct.obj (.cinit:_EPWM) 00080025 00000011 F2837xS_struct.obj (.cinit:_ECAP) 00080036 0000000e rts2800_fpu32.lib : exit.c.obj (.cinit) 00080044 0000000b F2837xS_struct.obj (.cinit:_EQEP) 0008004f 0000000b F2837xS_struct.obj (.cinit:_SPI) 0008005a 00000009 F2837xS_struct.obj (.cinit:_SDFM) 00080063 00000007 F2837xS_struct.obj (.cinit:_I2C) 0008006a 00000007 F2837xS_struct.obj (.cinit:_MCBSP) 00080071 00000007 F2837xS_struct.obj (.cinit:_SCI) 00080078 00000005 rts2800_fpu32.lib : _lock.c.obj (.cinit:__lock) 0008007d 00000005 : _lock.c.obj (.cinit:__unlock) 00080082 00000004 F2837xS_sci_io.obj (.cinit) 00080086 00000004 main.obj (.cinit) 0008008a 00000002 --HOLE-- [fill = 0] .pinit 0 00080008 00000000 UNINITIALIZED codestart * 0 00080000 00000002 00080000 00000002 F2837xS_CodeStartBranch.obj (codestart) .TI.ramfunc * 0 00086000 00000072 RUN ADDR = 00008000 00086000 0000006e F2837xS_SysCtrl.obj (.TI.ramfunc) 0008606e 00000004 F2837xS_usDelay.obj (.TI.ramfunc) .stack 1 00000400 00000100 UNINITIALIZED 00000400 00000100 --HOLE-- .reset 0 003fffc0 00000002 DSECT 003fffc0 00000002 rts2800_fpu32.lib : boot28.asm.obj (.reset) .econst 0 00090000 000001c0 00090000 000001c0 F2837xS_PieVect.obj (.econst:_PieVectTableInit) AdcaResultFile * 1 00000b00 00000018 UNINITIALIZED 00000b00 00000018 F2837xS_GlobalVariableDefs.obj (AdcaResultFile) AdcbResultFile * 1 00000b20 00000018 UNINITIALIZED 00000b20 00000018 F2837xS_GlobalVariableDefs.obj (AdcbResultFile) AdccResultFile * 1 00000b40 00000018 UNINITIALIZED 00000b40 00000018 F2837xS_GlobalVariableDefs.obj (AdccResultFile) AdcdResultFile * 1 00000b60 00000018 UNINITIALIZED 00000b60 00000018 F2837xS_GlobalVariableDefs.obj (AdcdResultFile) CpuTimer0RegsFile * 1 00000c00 00000008 UNINITIALIZED 00000c00 00000008 F2837xS_GlobalVariableDefs.obj (CpuTimer0RegsFile) CpuTimer1RegsFile * 1 00000c08 00000008 UNINITIALIZED 00000c08 00000008 F2837xS_GlobalVariableDefs.obj (CpuTimer1RegsFile) CpuTimer2RegsFile * 1 00000c10 00000008 UNINITIALIZED 00000c10 00000008 F2837xS_GlobalVariableDefs.obj (CpuTimer2RegsFile) PieCtrlRegsFile * 1 00000ce0 0000001a UNINITIALIZED 00000ce0 0000001a F2837xS_GlobalVariableDefs.obj (PieCtrlRegsFile) PieVectTableFile * 1 00000d00 000001c0 UNINITIALIZED 00000d00 000001c0 F2837xS_GlobalVariableDefs.obj (PieVectTableFile) EmuKeyVar * 1 00000d00 00000001 UNINITIALIZED 00000d00 00000001 F2837xS_GlobalVariableDefs.obj (EmuKeyVar) EmuBModeVar * 1 00000d01 00000001 UNINITIALIZED 00000d01 00000001 F2837xS_GlobalVariableDefs.obj (EmuBModeVar) FlashCallbackVar * 1 00000d02 00000000 UNINITIALIZED FlashScalingVar * 1 00000d02 00000000 UNINITIALIZED DmaRegsFile * 1 00001000 000000e0 UNINITIALIZED 00001000 000000e0 F2837xS_GlobalVariableDefs.obj (DmaRegsFile) Cla1RegsFile * 1 00001400 0000003e UNINITIALIZED 00001400 0000003e F2837xS_GlobalVariableDefs.obj (Cla1RegsFile) EPwm1RegsFile * 1 00004000 00000100 UNINITIALIZED 00004000 00000100 F2837xS_GlobalVariableDefs.obj (EPwm1RegsFile) EPwm2RegsFile * 1 00004100 00000100 UNINITIALIZED 00004100 00000100 F2837xS_GlobalVariableDefs.obj (EPwm2RegsFile) EPwm3RegsFile * 1 00004200 00000100 UNINITIALIZED 00004200 00000100 F2837xS_GlobalVariableDefs.obj (EPwm3RegsFile) EPwm4RegsFile * 1 00004300 00000100 UNINITIALIZED 00004300 00000100 F2837xS_GlobalVariableDefs.obj (EPwm4RegsFile) EPwm5RegsFile * 1 00004400 00000100 UNINITIALIZED 00004400 00000100 F2837xS_GlobalVariableDefs.obj (EPwm5RegsFile) EPwm6RegsFile * 1 00004500 00000100 UNINITIALIZED 00004500 00000100 F2837xS_GlobalVariableDefs.obj (EPwm6RegsFile) EPwm7RegsFile * 1 00004600 00000100 UNINITIALIZED 00004600 00000100 F2837xS_GlobalVariableDefs.obj (EPwm7RegsFile) EPwm8RegsFile * 1 00004700 00000100 UNINITIALIZED 00004700 00000100 F2837xS_GlobalVariableDefs.obj (EPwm8RegsFile) EPwm9RegsFile * 1 00004800 00000100 UNINITIALIZED 00004800 00000100 F2837xS_GlobalVariableDefs.obj (EPwm9RegsFile) EPwm10RegsFile * 1 00004900 00000100 UNINITIALIZED 00004900 00000100 F2837xS_GlobalVariableDefs.obj (EPwm10RegsFile) EPwm11RegsFile * 1 00004a00 00000100 UNINITIALIZED 00004a00 00000100 F2837xS_GlobalVariableDefs.obj (EPwm11RegsFile) EPwm12RegsFile * 1 00004b00 00000100 UNINITIALIZED 00004b00 00000100 F2837xS_GlobalVariableDefs.obj (EPwm12RegsFile) ECap1RegsFile * 1 00005000 00000020 UNINITIALIZED 00005000 00000020 F2837xS_GlobalVariableDefs.obj (ECap1RegsFile) ECap2RegsFile * 1 00005020 00000020 UNINITIALIZED 00005020 00000020 F2837xS_GlobalVariableDefs.obj (ECap2RegsFile) ECap3RegsFile * 1 00005040 00000020 UNINITIALIZED 00005040 00000020 F2837xS_GlobalVariableDefs.obj (ECap3RegsFile) ECap4RegsFile * 1 00005060 00000020 UNINITIALIZED 00005060 00000020 F2837xS_GlobalVariableDefs.obj (ECap4RegsFile) ECap5RegsFile * 1 00005080 00000020 UNINITIALIZED 00005080 00000020 F2837xS_GlobalVariableDefs.obj (ECap5RegsFile) ECap6RegsFile * 1 000050a0 00000020 UNINITIALIZED 000050a0 00000020 F2837xS_GlobalVariableDefs.obj (ECap6RegsFile) EQep1RegsFile * 1 00005100 00000022 UNINITIALIZED 00005100 00000022 F2837xS_GlobalVariableDefs.obj (EQep1RegsFile) EQep2RegsFile * 1 00005140 00000022 UNINITIALIZED 00005140 00000022 F2837xS_GlobalVariableDefs.obj (EQep2RegsFile) EQep3RegsFile * 1 00005180 00000022 UNINITIALIZED 00005180 00000022 F2837xS_GlobalVariableDefs.obj (EQep3RegsFile) DacaRegsFile * 1 00005c00 00000008 UNINITIALIZED 00005c00 00000008 F2837xS_GlobalVariableDefs.obj (DacaRegsFile) DacbRegsFile * 1 00005c10 00000008 UNINITIALIZED 00005c10 00000008 F2837xS_GlobalVariableDefs.obj (DacbRegsFile) DaccRegsFile * 1 00005c20 00000008 UNINITIALIZED 00005c20 00000008 F2837xS_GlobalVariableDefs.obj (DaccRegsFile) Sdfm1RegsFile * 1 00005e00 00000080 UNINITIALIZED 00005e00 00000080 F2837xS_GlobalVariableDefs.obj (Sdfm1RegsFile) Sdfm2RegsFile * 1 00005e80 00000080 UNINITIALIZED 00005e80 00000080 F2837xS_GlobalVariableDefs.obj (Sdfm2RegsFile) McbspaRegsFile * 1 00006000 00000024 UNINITIALIZED 00006000 00000024 F2837xS_GlobalVariableDefs.obj (McbspaRegsFile) McbspbRegsFile * 1 00006040 00000024 UNINITIALIZED 00006040 00000024 F2837xS_GlobalVariableDefs.obj (McbspbRegsFile) SpiaRegsFile * 1 00006100 00000010 UNINITIALIZED 00006100 00000010 F2837xS_GlobalVariableDefs.obj (SpiaRegsFile) SpibRegsFile * 1 00006110 00000010 UNINITIALIZED 00006110 00000010 F2837xS_GlobalVariableDefs.obj (SpibRegsFile) SpicRegsFile * 1 00006120 00000010 UNINITIALIZED 00006120 00000010 F2837xS_GlobalVariableDefs.obj (SpicRegsFile) UppRegsFile * 1 00006200 00000048 UNINITIALIZED 00006200 00000048 F2837xS_GlobalVariableDefs.obj (UppRegsFile) WdRegsFile * 1 00007000 0000002b UNINITIALIZED 00007000 0000002b F2837xS_GlobalVariableDefs.obj (WdRegsFile) NmiIntruptRegsFile * 1 00007060 00000007 UNINITIALIZED 00007060 00000007 F2837xS_GlobalVariableDefs.obj (NmiIntruptRegsFile) XintRegsFile * 1 00007070 0000000b UNINITIALIZED 00007070 0000000b F2837xS_GlobalVariableDefs.obj (XintRegsFile) SciaRegsFile * 1 00007200 00000010 UNINITIALIZED 00007200 00000010 F2837xS_GlobalVariableDefs.obj (SciaRegsFile) ScibRegsFile * 1 00007210 00000010 UNINITIALIZED 00007210 00000010 F2837xS_GlobalVariableDefs.obj (ScibRegsFile) ScicRegsFile * 1 00007220 00000010 UNINITIALIZED 00007220 00000010 F2837xS_GlobalVariableDefs.obj (ScicRegsFile) ScidRegsFile * 1 00007230 00000010 UNINITIALIZED 00007230 00000010 F2837xS_GlobalVariableDefs.obj (ScidRegsFile) I2caRegsFile * 1 00007300 00000022 UNINITIALIZED 00007300 00000022 F2837xS_GlobalVariableDefs.obj (I2caRegsFile) I2cbRegsFile * 1 00007340 00000022 UNINITIALIZED 00007340 00000022 F2837xS_GlobalVariableDefs.obj (I2cbRegsFile) AdcaRegsFile * 1 00007400 00000080 UNINITIALIZED 00007400 00000080 F2837xS_GlobalVariableDefs.obj (AdcaRegsFile) AdcbRegsFile * 1 00007480 00000080 UNINITIALIZED 00007480 00000080 F2837xS_GlobalVariableDefs.obj (AdcbRegsFile) AdccRegsFile * 1 00007500 00000080 UNINITIALIZED 00007500 00000080 F2837xS_GlobalVariableDefs.obj (AdccRegsFile) AdcdRegsFile * 1 00007580 00000080 UNINITIALIZED 00007580 00000080 F2837xS_GlobalVariableDefs.obj (AdcdRegsFile) CanaRegsFile * 1 00048000 00000164 UNINITIALIZED 00048000 00000164 F2837xS_GlobalVariableDefs.obj (CanaRegsFile) CanbRegsFile * 1 0004a000 00000164 UNINITIALIZED 0004a000 00000164 F2837xS_GlobalVariableDefs.obj (CanbRegsFile) AnalogSubsysRegsFile * 1 0005d180 00000048 UNINITIALIZED 0005d180 00000048 F2837xS_GlobalVariableDefs.obj (AnalogSubsysRegsFile) Cla1SoftIntRegsFile * 1 00000ce0 00000004 DSECT 00000ce0 00000004 F2837xS_GlobalVariableDefs.obj (Cla1SoftIntRegsFile) Cmpss1RegsFile * 1 00005c80 00000020 UNINITIALIZED 00005c80 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss1RegsFile) Cmpss2RegsFile * 1 00005ca0 00000020 UNINITIALIZED 00005ca0 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss2RegsFile) Cmpss3RegsFile * 1 00005cc0 00000020 UNINITIALIZED 00005cc0 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss3RegsFile) Cmpss4RegsFile * 1 00005ce0 00000020 UNINITIALIZED 00005ce0 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss4RegsFile) Cmpss5RegsFile * 1 00005d00 00000020 UNINITIALIZED 00005d00 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss5RegsFile) Cmpss6RegsFile * 1 00005d20 00000020 UNINITIALIZED 00005d20 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss6RegsFile) Cmpss7RegsFile * 1 00005d40 00000020 UNINITIALIZED 00005d40 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss7RegsFile) Cmpss8RegsFile * 1 00005d60 00000020 UNINITIALIZED 00005d60 00000020 F2837xS_GlobalVariableDefs.obj (Cmpss8RegsFile) InputXbarRegsFile * 1 00007900 00000020 UNINITIALIZED 00007900 00000020 F2837xS_GlobalVariableDefs.obj (InputXbarRegsFile) XbarRegsFile * 1 00007920 00000020 UNINITIALIZED 00007920 00000020 F2837xS_GlobalVariableDefs.obj (XbarRegsFile) SyncSocRegsFile * 1 00007940 00000006 UNINITIALIZED 00007940 00000006 F2837xS_GlobalVariableDefs.obj (SyncSocRegsFile) DmaClaSrcSelRegsFile * 1 00007980 0000001a UNINITIALIZED 00007980 0000001a F2837xS_GlobalVariableDefs.obj (DmaClaSrcSelRegsFile) EPwmXbarRegsFile * 1 00007a00 00000040 UNINITIALIZED 00007a00 00000040 F2837xS_GlobalVariableDefs.obj (EPwmXbarRegsFile) OutputXbarRegsFile * 1 00007a80 00000040 UNINITIALIZED 00007a80 00000040 F2837xS_GlobalVariableDefs.obj (OutputXbarRegsFile) GpioCtrlRegsFile * 1 00007c00 00000180 UNINITIALIZED 00007c00 00000180 F2837xS_GlobalVariableDefs.obj (GpioCtrlRegsFile) GpioDataRegsFile * 1 00007f00 00000030 UNINITIALIZED 00007f00 00000030 F2837xS_GlobalVariableDefs.obj (GpioDataRegsFile) Emif1RegsFile * 1 00047000 00000070 UNINITIALIZED 00047000 00000070 F2837xS_GlobalVariableDefs.obj (Emif1RegsFile) Emif2RegsFile * 1 00047800 00000070 UNINITIALIZED 00047800 00000070 F2837xS_GlobalVariableDefs.obj (Emif2RegsFile) FlashPumpSemaphoreRegsFile * 1 00050024 00000002 UNINITIALIZED 00050024 00000002 F2837xS_GlobalVariableDefs.obj (FlashPumpSemaphoreRegsFile) RomPrefetchRegsFile * 1 0005e608 00000002 UNINITIALIZED 0005e608 00000002 F2837xS_GlobalVariableDefs.obj (RomPrefetchRegsFile) DcsmZ1RegsFile * 1 0005f000 00000024 UNINITIALIZED 0005f000 00000024 F2837xS_GlobalVariableDefs.obj (DcsmZ1RegsFile) DcsmZ2RegsFile * 1 0005f040 00000024 UNINITIALIZED 0005f040 00000024 F2837xS_GlobalVariableDefs.obj (DcsmZ2RegsFile) DcsmCommonRegsFile * 1 0005f070 00000008 UNINITIALIZED 0005f070 00000008 F2837xS_GlobalVariableDefs.obj (DcsmCommonRegsFile) MemCfgRegsFile * 1 0005f400 00000080 UNINITIALIZED 0005f400 00000080 F2837xS_GlobalVariableDefs.obj (MemCfgRegsFile) Emif1ConfigRegsFile * 1 0005f480 00000020 UNINITIALIZED 0005f480 00000020 F2837xS_GlobalVariableDefs.obj (Emif1ConfigRegsFile) Emif2ConfigRegsFile * 1 0005f4a0 00000020 UNINITIALIZED 0005f4a0 00000020 F2837xS_GlobalVariableDefs.obj (Emif2ConfigRegsFile) AccessProtectionRegsFile * 1 0005f4c0 00000040 UNINITIALIZED 0005f4c0 00000040 F2837xS_GlobalVariableDefs.obj (AccessProtectionRegsFile) MemoryErrorRegsFile * 1 0005f500 00000040 UNINITIALIZED 0005f500 00000040 F2837xS_GlobalVariableDefs.obj (MemoryErrorRegsFile) RomWaitStateRegsFile * 1 0005f540 00000002 UNINITIALIZED 0005f540 00000002 F2837xS_GlobalVariableDefs.obj (RomWaitStateRegsFile) Flash0CtrlRegsFile * 1 0005f800 00000182 UNINITIALIZED 0005f800 00000182 F2837xS_GlobalVariableDefs.obj (Flash0CtrlRegsFile) Flash0EccRegsFile * 1 0005fb00 00000028 UNINITIALIZED 0005fb00 00000028 F2837xS_GlobalVariableDefs.obj (Flash0EccRegsFile) Flash1CtrlRegsFile * 1 0005fc00 00000182 UNINITIALIZED 0005fc00 00000182 F2837xS_GlobalVariableDefs.obj (Flash1CtrlRegsFile) Flash1EccRegsFile * 1 0005ff00 00000028 UNINITIALIZED 0005ff00 00000028 F2837xS_GlobalVariableDefs.obj (Flash1EccRegsFile) DcsmZ1OtpFile * 1 00078000 00000020 NOLOAD SECTION 00078000 00000020 F2837xS_GlobalVariableDefs.obj (DcsmZ1OtpFile) DcsmZ2OtpFile * 1 00078200 00000020 NOLOAD SECTION 00078200 00000020 F2837xS_GlobalVariableDefs.obj (DcsmZ2OtpFile) DevCfgRegsFile * 1 0005d000 0000012e UNINITIALIZED 0005d000 0000012e F2837xS_GlobalVariableDefs.obj (DevCfgRegsFile) ClkCfgRegsFile * 1 0005d200 00000032 UNINITIALIZED 0005d200 00000032 F2837xS_GlobalVariableDefs.obj (ClkCfgRegsFile) CpuSysRegsFile * 1 0005d300 00000082 UNINITIALIZED 0005d300 00000082 F2837xS_GlobalVariableDefs.obj (CpuSysRegsFile) .text 0 00082000 00000dd5 00082000 00000585 F2837xS_DefaultISR.obj (.text:retain) 00082585 00000345 F2837xS_SysCtrl.obj (.text) 000828ca 00000244 F2837xS_Gpio.obj (.text) 00082b0e 00000088 rts2800_fpu32.lib : fs_div28.asm.obj (.text) 00082b96 00000087 main.obj (.text) 00082c1d 0000007c F2837xS_CpuTimers.obj (.text) 00082c99 00000056 rts2800_fpu32.lib : boot28.asm.obj (.text) 00082cef 00000029 : exit.c.obj (.text) 00082d18 00000028 F2837xS_PieCtrl.obj (.text) 00082d40 00000026 F2837xS_PieVect.obj (.text) 00082d66 00000024 rts2800_fpu32.lib : cpy_tbl.c.obj (.text) 00082d8a 0000001d : memcpy.c.obj (.text) 00082da7 00000012 : args_main.c.obj (.text) 00082db9 0000000d main.obj (.text:retain) 00082dc6 00000009 rts2800_fpu32.lib : _lock.c.obj (.text) 00082dcf 00000003 F2837xS_DBGIER.obj (.text) 00082dd2 00000002 rts2800_fpu32.lib : pre_init.c.obj (.text) 00082dd4 00000001 : startup.c.obj (.text) .ebss 1 0000a800 00000074 UNINITIALIZED 0000a800 0000001a F2837xS_struct.obj (.ebss:_EPWM) 0000a81a 00000018 F2837xS_CpuTimers.obj (.ebss) 0000a832 0000000e F2837xS_struct.obj (.ebss:_ECAP) 0000a840 00000008 F2837xS_struct.obj (.ebss:_EQEP) 0000a848 00000008 F2837xS_struct.obj (.ebss:_SPI) 0000a850 00000006 F2837xS_TempSensorConv.obj (.ebss) 0000a856 00000006 F2837xS_struct.obj (.ebss:_SDFM) 0000a85c 00000006 rts2800_fpu32.lib : exit.c.obj (.ebss) 0000a862 00000004 F2837xS_struct.obj (.ebss:_I2C) 0000a866 00000004 F2837xS_struct.obj (.ebss:_MCBSP) 0000a86a 00000004 F2837xS_struct.obj (.ebss:_SCI) 0000a86e 00000002 rts2800_fpu32.lib : _lock.c.obj (.ebss:__lock) 0000a870 00000002 : _lock.c.obj (.ebss:__unlock) 0000a872 00000001 F2837xS_sci_io.obj (.ebss) 0000a873 00000001 main.obj (.ebss) MODULE SUMMARY Module code initialized data uninitialized data ------ ---- ---------------- ------------------ .\ main.obj 148 4 1 +--+--------------------------------+------+------------------+--------------------+ Total: 148 4 1 .\included_files\ F2837xS_GlobalVariableDefs.obj 0 0 9149 F2837xS_DefaultISR.obj 1413 0 0 F2837xS_SysCtrl.obj 1057 0 0 F2837xS_Gpio.obj 580 0 0 F2837xS_PieVect.obj 38 448 0 F2837xS_struct.obj 0 98 74 F2837xS_CpuTimers.obj 124 0 24 F2837xS_PieCtrl.obj 40 0 0 F2837xS_usDelay.obj 8 0 0 F2837xS_TempSensorConv.obj 0 0 6 F2837xS_sci_io.obj 0 4 1 F2837xS_DBGIER.obj 3 0 0 F2837xS_CodeStartBranch.obj 2 0 0 +--+--------------------------------+------+------------------+--------------------+ Total: 3265 550 9254 C:\ti\ccs1011\ccs\tools\compiler\lib\rts2800_fpu32.lib fs_div28.asm.obj 136 0 0 boot28.asm.obj 86 0 0 exit.c.obj 41 14 6 cpy_tbl.c.obj 36 0 0 memcpy.c.obj 29 0 0 _lock.c.obj 9 10 4 args_main.c.obj 18 0 0 pre_init.c.obj 2 0 0 startup.c.obj 1 0 0 +--+--------------------------------+------+------------------+--------------------+ Total: 358 24 10 Stack: 0 0 256 +--+--------------------------------+------+------------------+--------------------+ Grand Total: 3771 578 9521 GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE address data page name -------- ---------------- ---- 00000400 10 (00000400) __stack 00000b00 2c (00000b00) _AdcaResultRegs 00000b20 2c (00000b00) _AdcbResultRegs 00000b40 2d (00000b40) _AdccResultRegs 00000b60 2d (00000b40) _AdcdResultRegs 00000c00 30 (00000c00) _CpuTimer0Regs 00000c08 30 (00000c00) _CpuTimer1Regs 00000c10 30 (00000c00) _CpuTimer2Regs 00000ce0 33 (00000cc0) _Cla1SoftIntRegs 00000ce0 33 (00000cc0) _PieCtrlRegs 00000d00 34 (00000d00) _EmuKey 00000d00 34 (00000d00) _PieVectTable 00000d01 34 (00000d00) _EmuBMode 00001000 40 (00001000) _DmaRegs 00001400 50 (00001400) _Cla1Regs 00004000 100 (00004000) _EPwm1Regs 00004100 104 (00004100) _EPwm2Regs 00004200 108 (00004200) _EPwm3Regs 00004300 10c (00004300) _EPwm4Regs 00004400 110 (00004400) _EPwm5Regs 00004500 114 (00004500) _EPwm6Regs 00004600 118 (00004600) _EPwm7Regs 00004700 11c (00004700) _EPwm8Regs 00004800 120 (00004800) _EPwm9Regs 00004900 124 (00004900) _EPwm10Regs 00004a00 128 (00004a00) _EPwm11Regs 00004b00 12c (00004b00) _EPwm12Regs 00005000 140 (00005000) _ECap1Regs 00005020 140 (00005000) _ECap2Regs 00005040 141 (00005040) _ECap3Regs 00005060 141 (00005040) _ECap4Regs 00005080 142 (00005080) _ECap5Regs 000050a0 142 (00005080) _ECap6Regs 00005100 144 (00005100) _EQep1Regs 00005140 145 (00005140) _EQep2Regs 00005180 146 (00005180) _EQep3Regs 00005c00 170 (00005c00) _DacaRegs 00005c10 170 (00005c00) _DacbRegs 00005c20 170 (00005c00) _DaccRegs 00005c80 172 (00005c80) _Cmpss1Regs 00005ca0 172 (00005c80) _Cmpss2Regs 00005cc0 173 (00005cc0) _Cmpss3Regs 00005ce0 173 (00005cc0) _Cmpss4Regs 00005d00 174 (00005d00) _Cmpss5Regs 00005d20 174 (00005d00) _Cmpss6Regs 00005d40 175 (00005d40) _Cmpss7Regs 00005d60 175 (00005d40) _Cmpss8Regs 00005e00 178 (00005e00) _Sdfm1Regs 00005e80 17a (00005e80) _Sdfm2Regs 00006000 180 (00006000) _McbspaRegs 00006040 181 (00006040) _McbspbRegs 00006100 184 (00006100) _SpiaRegs 00006110 184 (00006100) _SpibRegs 00006120 184 (00006100) _SpicRegs 00006200 188 (00006200) _UppRegs 00007000 1c0 (00007000) _WdRegs 00007060 1c1 (00007040) _NmiIntruptRegs 00007070 1c1 (00007040) _XintRegs 00007200 1c8 (00007200) _SciaRegs 00007210 1c8 (00007200) _ScibRegs 00007220 1c8 (00007200) _ScicRegs 00007230 1c8 (00007200) _ScidRegs 00007300 1cc (00007300) _I2caRegs 00007340 1cd (00007340) _I2cbRegs 00007400 1d0 (00007400) _AdcaRegs 00007480 1d2 (00007480) _AdcbRegs 00007500 1d4 (00007500) _AdccRegs 00007580 1d6 (00007580) _AdcdRegs 00007900 1e4 (00007900) _InputXbarRegs 00007920 1e4 (00007900) _XbarRegs 00007940 1e5 (00007940) _SyncSocRegs 00007980 1e6 (00007980) _DmaClaSrcSelRegs 00007a00 1e8 (00007a00) _EPwmXbarRegs 00007a80 1ea (00007a80) _OutputXbarRegs 00007c00 1f0 (00007c00) _GpioCtrlRegs 00007f00 1fc (00007f00) _GpioDataRegs 0000a800 2a0 (0000a800) _EPWM 0000a81a 2a0 (0000a800) _CpuTimer0 0000a822 2a0 (0000a800) _CpuTimer1 0000a82a 2a0 (0000a800) _CpuTimer2 0000a832 2a0 (0000a800) _ECAP 0000a840 2a1 (0000a840) _EQEP 0000a848 2a1 (0000a840) _SPI 0000a850 2a1 (0000a840) _tempSensor_tempSlope 0000a852 2a1 (0000a840) _tempSensor_tempOffset 0000a854 2a1 (0000a840) _tempSensor_scaleFactor 0000a856 2a1 (0000a840) _SDFM 0000a85c 2a1 (0000a840) ___TI_enable_exit_profile_output 0000a85e 2a1 (0000a840) ___TI_cleanup_ptr 0000a860 2a1 (0000a840) ___TI_dtors_ptr 0000a862 2a1 (0000a840) _I2C 0000a866 2a1 (0000a840) _MCBSP 0000a86a 2a1 (0000a840) _SCI 0000a86e 2a1 (0000a840) __lock 0000a870 2a1 (0000a840) __unlock 0000a872 2a1 (0000a840) _deviceOpen 0000a873 2a1 (0000a840) _a 00047000 11c0 (00047000) _Emif1Regs 00047800 11e0 (00047800) _Emif2Regs 00048000 1200 (00048000) _CanaRegs 0004a000 1280 (0004a000) _CanbRegs 00050024 1400 (00050000) _FlashPumpSemaphoreRegs 0005d000 1740 (0005d000) _DevCfgRegs 0005d180 1746 (0005d180) _AnalogSubsysRegs 0005d200 1748 (0005d200) _ClkCfgRegs 0005d300 174c (0005d300) _CpuSysRegs 0005e608 1798 (0005e600) _RomPrefetchRegs 0005f000 17c0 (0005f000) _DcsmZ1Regs 0005f040 17c1 (0005f040) _DcsmZ2Regs 0005f070 17c1 (0005f040) _DcsmCommonRegs 0005f400 17d0 (0005f400) _MemCfgRegs 0005f480 17d2 (0005f480) _Emif1ConfigRegs 0005f4a0 17d2 (0005f480) _Emif2ConfigRegs 0005f4c0 17d3 (0005f4c0) _AccessProtectionRegs 0005f500 17d4 (0005f500) _MemoryErrorRegs 0005f540 17d5 (0005f540) _RomWaitStateRegs 0005f800 17e0 (0005f800) _Flash0CtrlRegs 0005fb00 17ec (0005fb00) _Flash0EccRegs 0005fc00 17f0 (0005fc00) _Flash1CtrlRegs 0005ff00 17fc (0005ff00) _Flash1EccRegs 00078000 1e00 (00078000) _DcsmZ1Otp 00078200 1e08 (00078200) _DcsmZ2Otp 00090000 2400 (00090000) _PieVectTableInit GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name page address name ---- ------- ---- abs ffffffff .text 0 00082cef C$$EXIT 0 00082b0e FS$$DIV 0 000820be _ADCA1_ISR 0 0008233e _ADCA2_ISR 0 00082348 _ADCA3_ISR 0 00082352 _ADCA4_ISR 0 00082334 _ADCA_EVT_ISR 0 000820c8 _ADCB1_ISR 0 00082366 _ADCB2_ISR 0 00082370 _ADCB3_ISR 0 0008237a _ADCB4_ISR 0 0008235c _ADCB_EVT_ISR 0 000820d2 _ADCC1_ISR 0 000824ce _ADCC2_ISR 0 000824d8 _ADCC3_ISR 0 000824e2 _ADCC4_ISR 0 000824c4 _ADCC_EVT_ISR 0 000820f0 _ADCD1_ISR 0 000824f6 _ADCD2_ISR 0 00082500 _ADCD3_ISR 0 0008250a _ADCD4_ISR 0 000824ec _ADCD_EVT_ISR 0 00082546 _AUX_PLL_SLIP_ISR 1 0005f4c0 _AccessProtectionRegs 1 00007400 _AdcaRegs 1 00000b00 _AdcaResultRegs 1 00007480 _AdcbRegs 1 00000b20 _AdcbResultRegs 1 00007500 _AdccRegs 1 00000b40 _AdccResultRegs 1 00007580 _AdcdRegs 1 00000b60 _AdcdResultRegs 1 0005d180 _AnalogSubsysRegs 0 00082887 _AuxAuxClkSel 0 00082871 _AuxIntOsc2Sel 0 0008287b _AuxXtalOscSel 0 0008230c _CANA0_ISR 0 00082316 _CANA1_ISR 0 00082320 _CANB0_ISR 0 0008232a _CANB1_ISR 0 00082384 _CLA1_1_ISR 0 0008238e _CLA1_2_ISR 0 00082398 _CLA1_3_ISR 0 000823a2 _CLA1_4_ISR 0 000823ac _CLA1_5_ISR 0 000823b6 _CLA1_6_ISR 0 000823c0 _CLA1_7_ISR 0 000823ca _CLA1_8_ISR 0 00082550 _CLA_OVERFLOW_ISR 0 0008255a _CLA_UNDERFLOW_ISR 1 00048000 _CanaRegs 1 0004a000 _CanbRegs 1 00001400 _Cla1Regs 0 00000ce0 _Cla1SoftIntRegs 1 0005d200 _ClkCfgRegs 1 00005c80 _Cmpss1Regs 1 00005ca0 _Cmpss2Regs 1 00005cc0 _Cmpss3Regs 1 00005ce0 _Cmpss4Regs 1 00005d00 _Cmpss5Regs 1 00005d20 _Cmpss6Regs 1 00005d40 _Cmpss7Regs 1 00005d60 _Cmpss8Regs 0 00082c5e _ConfigCpuTimer 1 0005d300 _CpuSysRegs 1 0000a81a _CpuTimer0 1 00000c00 _CpuTimer0Regs 1 0000a822 _CpuTimer1 1 00000c08 _CpuTimer1Regs 1 0000a82a _CpuTimer2 1 00000c10 _CpuTimer2Regs 0 00082830 _CsmUnlock 0 00082014 _DATALOG_ISR 0 00082258 _DMA_CH1_ISR 0 00082262 _DMA_CH2_ISR 0 0008226c _DMA_CH3_ISR 0 00082276 _DMA_CH4_ISR 0 00082280 _DMA_CH5_ISR 0 0008228a _DMA_CH6_ISR 1 00005c00 _DacaRegs 1 00005c10 _DacbRegs 1 00005c20 _DaccRegs 1 0005f070 _DcsmCommonRegs 1 00078000 _DcsmZ1Otp 1 0005f000 _DcsmZ1Regs 1 00078200 _DcsmZ2Otp 1 0005f040 _DcsmZ2Regs 1 0005d000 _DevCfgRegs 0 00082694 _DisableDog 0 00082646 _DisablePeripheralClocks 1 00007980 _DmaClaSrcSelRegs 1 00001000 _DmaRegs 1 0000a832 _ECAP 0 000821ae _ECAP1_ISR 0 000821b8 _ECAP2_ISR 0 000821c2 _ECAP3_ISR 0 000821cc _ECAP4_ISR 0 000821d6 _ECAP5_ISR 0 000821e0 _ECAP6_ISR 1 00005000 _ECap1Regs 1 00005020 _ECap2Regs 1 00005040 _ECap3Regs 1 00005060 _ECap4Regs 1 00005080 _ECap5Regs 1 000050a0 _ECap6Regs 0 00082514 _EMIF_ERROR_ISR 0 0008256e _EMPTY_ISR 0 00082028 _EMU_ISR 1 0000a800 _EPWM 0 0008246a _EPWM10_ISR 0 00082442 _EPWM10_TZ_ISR 0 00082474 _EPWM11_ISR 0 0008244c _EPWM11_TZ_ISR 0 0008247e _EPWM12_ISR 0 00082456 _EPWM12_TZ_ISR 0 0008215e _EPWM1_ISR 0 0008210e _EPWM1_TZ_ISR 0 00082168 _EPWM2_ISR 0 00082118 _EPWM2_TZ_ISR 0 00082172 _EPWM3_ISR 0 00082122 _EPWM3_TZ_ISR 0 0008217c _EPWM4_ISR 0 0008212c _EPWM4_TZ_ISR 0 00082186 _EPWM5_ISR 0 00082136 _EPWM5_TZ_ISR 0 00082190 _EPWM6_ISR 0 00082140 _EPWM6_TZ_ISR 0 0008219a _EPWM7_ISR 0 0008214a _EPWM7_TZ_ISR 0 000821a4 _EPWM8_ISR 0 00082154 _EPWM8_TZ_ISR 0 00082460 _EPWM9_ISR 0 00082438 _EPWM9_TZ_ISR 1 00004900 _EPwm10Regs 1 00004a00 _EPwm11Regs 1 00004b00 _EPwm12Regs 1 00004000 _EPwm1Regs 1 00004100 _EPwm2Regs 1 00004200 _EPwm3Regs 1 00004300 _EPwm4Regs 1 00004400 _EPwm5Regs 1 00004500 _EPwm6Regs 1 00004600 _EPwm7Regs 1 00004700 _EPwm8Regs 1 00004800 _EPwm9Regs 1 00007a00 _EPwmXbarRegs 1 0000a840 _EQEP 0 000821ea _EQEP1_ISR 0 000821f4 _EQEP2_ISR 0 000821fe _EQEP3_ISR 1 00005100 _EQep1Regs 1 00005140 _EQep2Regs 1 00005180 _EQep3Regs 1 0005f480 _Emif1ConfigRegs 1 00047000 _Emif1Regs 1 0005f4a0 _Emif2ConfigRegs 1 00047800 _Emif2Regs 1 00000d01 _EmuBMode 1 00000d00 _EmuKey 0 00082d37 _EnableInterrupts 0 0000806e _F28x_usDelay 0 00082528 _FLASH_CORRECTABLE_ERROR_ISR 0 000823fc _FPU_OVERFLOW_ISR 0 00082406 _FPU_UNDERFLOW_ISR 1 0005f800 _Flash0CtrlRegs 1 0005fb00 _Flash0EccRegs 1 0005fc00 _Flash1CtrlRegs 1 0005ff00 _Flash1EccRegs 0 00008052 _FlashOff_Bank0 0 00008060 _FlashOff_Bank1 1 00050024 _FlashPumpSemaphoreRegs 0 00082ac3 _GPIO_EnableUnbondedIOPullups 0 00082a9e _GPIO_EnableUnbondedIOPullupsFor100Pin 0 00082a85 _GPIO_EnableUnbondedIOPullupsFor176Pin 0 00082ad9 _GPIO_ReadPin 0 00082a2a _GPIO_SetupLock 0 0008290a _GPIO_SetupPinMux 0 00082996 _GPIO_SetupPinOptions 0 00082a53 _GPIO_SetupXINT1Gpio 0 00082a5d _GPIO_SetupXINT2Gpio 0 00082a67 _GPIO_SetupXINT3Gpio 0 00082a71 _GPIO_SetupXINT4Gpio 0 00082a7b _GPIO_SetupXINT5Gpio 0 00082af0 _GPIO_WritePin 1 00007c00 _GpioCtrlRegs 1 00007f00 _GpioDataRegs 0 000828a5 _HALT 0 000828b6 _HIB 1 0000a862 _I2C 0 0008229e _I2CA_FIFO_ISR 0 00082294 _I2CA_ISR 0 000822b2 _I2CB_FIFO_ISR 0 000822a8 _I2CB_ISR 1 00007300 _I2caRegs 1 00007340 _I2cbRegs 0 00082891 _IDLE 0 0008203c _ILLEGAL_ISR 0 00082410 _IPC0_ISR 0 0008241a _IPC1_ISR 0 00082424 _IPC2_ISR 0 0008242e _IPC3_ISR 0 00082768 _InitAuxPll 0 00082c1d _InitCpuTimers 0 00008000 _InitFlash_Bank0 0 00008029 _InitFlash_Bank1 0 000828ca _InitGpio 0 000825c2 _InitPeripheralClocks 0 00082d18 _InitPieCtrl 0 00082d40 _InitPieVectTable 0 00082585 _InitSysCtrl 0 000826a2 _InitSysPll 1 00007900 _InputXbarRegs 1 0000a866 _MCBSP 0 00082230 _MCBSPA_RX_ISR 0 0008223a _MCBSPA_TX_ISR 0 00082244 _MCBSPB_RX_ISR 0 0008224e _MCBSPB_TX_ISR 1 00006000 _McbspaRegs 1 00006040 _McbspbRegs 1 0005f400 _MemCfgRegs 1 0005f500 _MemoryErrorRegs 0 00082032 _NMI_ISR 0 0008257b _NOTUSED_ISR 1 00007060 _NmiIntruptRegs 1 00007a80 _OutputXbarRegs 0 00082564 _PIE_RESERVED_ISR 1 00000ce0 _PieCtrlRegs 1 00000d00 _PieVectTable 0 00090000 _PieVectTableInit 0 00082532 _RAM_ACCESS_VIOLATION_ISR 0 0008251e _RAM_CORRECTABLE_ERROR_ISR 0 0008201e _RTOS_ISR 0 00086072 _RamfuncsLoadEnd abs 00000072 _RamfuncsLoadSize 0 00086000 _RamfuncsLoadStart 0 00008072 _RamfuncsRunEnd abs 00000072 _RamfuncsRunSize 0 00008000 _RamfuncsRunStart 0 0008267c _ReleaseFlashPump 1 0005e608 _RomPrefetchRegs 1 0005f540 _RomWaitStateRegs 1 0000a86a _SCI 0 000822e4 _SCIA_RX_ISR 0 000822ee _SCIA_TX_ISR 0 000822f8 _SCIB_RX_ISR 0 00082302 _SCIB_TX_ISR 0 000822bc _SCIC_RX_ISR 0 000822c6 _SCIC_TX_ISR 0 000822d0 _SCID_RX_ISR 0 000822da _SCID_TX_ISR 0 00082488 _SD1_ISR 0 00082492 _SD2_ISR 1 0000a856 _SDFM 1 0000a848 _SPI 0 00082208 _SPIA_RX_ISR 0 00082212 _SPIA_TX_ISR 0 0008221c _SPIB_RX_ISR 0 00082226 _SPIB_TX_ISR 0 0008249c _SPIC_RX_ISR 0 000824a6 _SPIC_TX_ISR 0 0008289a _STANDBY 0 0008253c _SYS_PLL_SLIP_ISR 1 00007200 _SciaRegs 1 00007210 _ScibRegs 1 00007220 _ScicRegs 1 00007230 _ScidRegs 1 00005e00 _Sdfm1Regs 1 00005e80 _Sdfm2Regs 0 0008265e _SeizeFlashPump_Bank0 0 0008266d _SeizeFlashPump_Bank1 0 00082686 _ServiceDog 0 00082dcf _SetDBGIER 1 00006100 _SpiaRegs 1 00006110 _SpibRegs 1 00006120 _SpicRegs 1 00007940 _SyncSocRegs 0 00082851 _SysIntOsc1Sel 0 0008285b _SysIntOsc2Sel 0 00082865 _SysXtalOscSel 0 000820fa _TIMER0_ISR 0 00082000 _TIMER1_ISR 0 0008200a _TIMER2_ISR 0 000824b0 _UPPA_ISR 0 000824ba _USBA_ISR 0 000820a0 _USER10_ISR 0 000820aa _USER11_ISR 0 000820b4 _USER12_ISR 0 00082046 _USER1_ISR 0 00082050 _USER2_ISR 0 0008205a _USER3_ISR 0 00082064 _USER4_ISR 0 0008206e _USER5_ISR 0 00082078 _USER6_ISR 0 00082082 _USER7_ISR 0 0008208c _USER8_ISR 0 00082096 _USER9_ISR 1 00006200 _UppRegs 0 000823f2 _VCU_ISR 0 00082104 _WAKE_ISR 1 00007000 _WdRegs 0 000820dc _XINT1_ISR 0 000820e6 _XINT2_ISR 0 000823d4 _XINT3_ISR 0 000823de _XINT4_ISR 0 000823e8 _XINT5_ISR 1 00007920 _XbarRegs 1 00007070 _XintRegs 1 00000500 __STACK_END abs 00000100 __STACK_SIZE 1 0000a85e ___TI_cleanup_ptr 1 0000a860 ___TI_dtors_ptr 1 0000a85c ___TI_enable_exit_profile_output abs ffffffff ___TI_pprof_out_hndl abs ffffffff ___TI_prof_data_size abs ffffffff ___TI_prof_data_start abs ffffffff ___binit__ abs ffffffff ___c_args__ 0 00080008 ___cinit__ abs ffffffff ___etext__ abs ffffffff ___pinit__ abs ffffffff ___text__ 0 00082da7 __args_main 1 0000a86e __lock 0 00082dce __nop 0 00082dca __register_lock 0 00082dc6 __register_unlock 1 00000400 __stack 0 00082dd4 __system_post_cinit 0 00082dd2 __system_pre_init 1 0000a870 __unlock 1 0000a873 _a 0 00082cef _abort 0 00082c99 _c_int00 0 00082d66 _copy_in 1 0000a872 _deviceOpen 0 00082cf1 _exit 0 00082b96 _main 0 00082d8a _memcpy 0 00082bec _sci_init 0 00082db9 _sciaRxFifoIsr 0 00082c11 _scib_TX 0 00082bdb _system_init 1 0000a854 _tempSensor_scaleFactor 1 0000a852 _tempSensor_tempOffset 1 0000a850 _tempSensor_tempSlope abs ffffffff binit 0 00080008 cinit 0 00080000 code_start abs ffffffff etext abs ffffffff pinit GLOBAL SYMBOLS: SORTED BY Symbol Address page address name ---- ------- ---- 0 00000ce0 _Cla1SoftIntRegs 0 00008000 _InitFlash_Bank0 0 00008000 _RamfuncsRunStart 0 00008029 _InitFlash_Bank1 0 00008052 _FlashOff_Bank0 0 00008060 _FlashOff_Bank1 0 0000806e _F28x_usDelay 0 00008072 _RamfuncsRunEnd 0 00080000 code_start 0 00080008 ___cinit__ 0 00080008 cinit 0 00082000 _TIMER1_ISR 0 0008200a _TIMER2_ISR 0 00082014 _DATALOG_ISR 0 0008201e _RTOS_ISR 0 00082028 _EMU_ISR 0 00082032 _NMI_ISR 0 0008203c _ILLEGAL_ISR 0 00082046 _USER1_ISR 0 00082050 _USER2_ISR 0 0008205a _USER3_ISR 0 00082064 _USER4_ISR 0 0008206e _USER5_ISR 0 00082078 _USER6_ISR 0 00082082 _USER7_ISR 0 0008208c _USER8_ISR 0 00082096 _USER9_ISR 0 000820a0 _USER10_ISR 0 000820aa _USER11_ISR 0 000820b4 _USER12_ISR 0 000820be _ADCA1_ISR 0 000820c8 _ADCB1_ISR 0 000820d2 _ADCC1_ISR 0 000820dc _XINT1_ISR 0 000820e6 _XINT2_ISR 0 000820f0 _ADCD1_ISR 0 000820fa _TIMER0_ISR 0 00082104 _WAKE_ISR 0 0008210e _EPWM1_TZ_ISR 0 00082118 _EPWM2_TZ_ISR 0 00082122 _EPWM3_TZ_ISR 0 0008212c _EPWM4_TZ_ISR 0 00082136 _EPWM5_TZ_ISR 0 00082140 _EPWM6_TZ_ISR 0 0008214a _EPWM7_TZ_ISR 0 00082154 _EPWM8_TZ_ISR 0 0008215e _EPWM1_ISR 0 00082168 _EPWM2_ISR 0 00082172 _EPWM3_ISR 0 0008217c _EPWM4_ISR 0 00082186 _EPWM5_ISR 0 00082190 _EPWM6_ISR 0 0008219a _EPWM7_ISR 0 000821a4 _EPWM8_ISR 0 000821ae _ECAP1_ISR 0 000821b8 _ECAP2_ISR 0 000821c2 _ECAP3_ISR 0 000821cc _ECAP4_ISR 0 000821d6 _ECAP5_ISR 0 000821e0 _ECAP6_ISR 0 000821ea _EQEP1_ISR 0 000821f4 _EQEP2_ISR 0 000821fe _EQEP3_ISR 0 00082208 _SPIA_RX_ISR 0 00082212 _SPIA_TX_ISR 0 0008221c _SPIB_RX_ISR 0 00082226 _SPIB_TX_ISR 0 00082230 _MCBSPA_RX_ISR 0 0008223a _MCBSPA_TX_ISR 0 00082244 _MCBSPB_RX_ISR 0 0008224e _MCBSPB_TX_ISR 0 00082258 _DMA_CH1_ISR 0 00082262 _DMA_CH2_ISR 0 0008226c _DMA_CH3_ISR 0 00082276 _DMA_CH4_ISR 0 00082280 _DMA_CH5_ISR 0 0008228a _DMA_CH6_ISR 0 00082294 _I2CA_ISR 0 0008229e _I2CA_FIFO_ISR 0 000822a8 _I2CB_ISR 0 000822b2 _I2CB_FIFO_ISR 0 000822bc _SCIC_RX_ISR 0 000822c6 _SCIC_TX_ISR 0 000822d0 _SCID_RX_ISR 0 000822da _SCID_TX_ISR 0 000822e4 _SCIA_RX_ISR 0 000822ee _SCIA_TX_ISR 0 000822f8 _SCIB_RX_ISR 0 00082302 _SCIB_TX_ISR 0 0008230c _CANA0_ISR 0 00082316 _CANA1_ISR 0 00082320 _CANB0_ISR 0 0008232a _CANB1_ISR 0 00082334 _ADCA_EVT_ISR 0 0008233e _ADCA2_ISR 0 00082348 _ADCA3_ISR 0 00082352 _ADCA4_ISR 0 0008235c _ADCB_EVT_ISR 0 00082366 _ADCB2_ISR 0 00082370 _ADCB3_ISR 0 0008237a _ADCB4_ISR 0 00082384 _CLA1_1_ISR 0 0008238e _CLA1_2_ISR 0 00082398 _CLA1_3_ISR 0 000823a2 _CLA1_4_ISR 0 000823ac _CLA1_5_ISR 0 000823b6 _CLA1_6_ISR 0 000823c0 _CLA1_7_ISR 0 000823ca _CLA1_8_ISR 0 000823d4 _XINT3_ISR 0 000823de _XINT4_ISR 0 000823e8 _XINT5_ISR 0 000823f2 _VCU_ISR 0 000823fc _FPU_OVERFLOW_ISR 0 00082406 _FPU_UNDERFLOW_ISR 0 00082410 _IPC0_ISR 0 0008241a _IPC1_ISR 0 00082424 _IPC2_ISR 0 0008242e _IPC3_ISR 0 00082438 _EPWM9_TZ_ISR 0 00082442 _EPWM10_TZ_ISR 0 0008244c _EPWM11_TZ_ISR 0 00082456 _EPWM12_TZ_ISR 0 00082460 _EPWM9_ISR 0 0008246a _EPWM10_ISR 0 00082474 _EPWM11_ISR 0 0008247e _EPWM12_ISR 0 00082488 _SD1_ISR 0 00082492 _SD2_ISR 0 0008249c _SPIC_RX_ISR 0 000824a6 _SPIC_TX_ISR 0 000824b0 _UPPA_ISR 0 000824ba _USBA_ISR 0 000824c4 _ADCC_EVT_ISR 0 000824ce _ADCC2_ISR 0 000824d8 _ADCC3_ISR 0 000824e2 _ADCC4_ISR 0 000824ec _ADCD_EVT_ISR 0 000824f6 _ADCD2_ISR 0 00082500 _ADCD3_ISR 0 0008250a _ADCD4_ISR 0 00082514 _EMIF_ERROR_ISR 0 0008251e _RAM_CORRECTABLE_ERROR_ISR 0 00082528 _FLASH_CORRECTABLE_ERROR_ISR 0 00082532 _RAM_ACCESS_VIOLATION_ISR 0 0008253c _SYS_PLL_SLIP_ISR 0 00082546 _AUX_PLL_SLIP_ISR 0 00082550 _CLA_OVERFLOW_ISR 0 0008255a _CLA_UNDERFLOW_ISR 0 00082564 _PIE_RESERVED_ISR 0 0008256e _EMPTY_ISR 0 0008257b _NOTUSED_ISR 0 00082585 _InitSysCtrl 0 000825c2 _InitPeripheralClocks 0 00082646 _DisablePeripheralClocks 0 0008265e _SeizeFlashPump_Bank0 0 0008266d _SeizeFlashPump_Bank1 0 0008267c _ReleaseFlashPump 0 00082686 _ServiceDog 0 00082694 _DisableDog 0 000826a2 _InitSysPll 0 00082768 _InitAuxPll 0 00082830 _CsmUnlock 0 00082851 _SysIntOsc1Sel 0 0008285b _SysIntOsc2Sel 0 00082865 _SysXtalOscSel 0 00082871 _AuxIntOsc2Sel 0 0008287b _AuxXtalOscSel 0 00082887 _AuxAuxClkSel 0 00082891 _IDLE 0 0008289a _STANDBY 0 000828a5 _HALT 0 000828b6 _HIB 0 000828ca _InitGpio 0 0008290a _GPIO_SetupPinMux 0 00082996 _GPIO_SetupPinOptions 0 00082a2a _GPIO_SetupLock 0 00082a53 _GPIO_SetupXINT1Gpio 0 00082a5d _GPIO_SetupXINT2Gpio 0 00082a67 _GPIO_SetupXINT3Gpio 0 00082a71 _GPIO_SetupXINT4Gpio 0 00082a7b _GPIO_SetupXINT5Gpio 0 00082a85 _GPIO_EnableUnbondedIOPullupsFor176Pin 0 00082a9e _GPIO_EnableUnbondedIOPullupsFor100Pin 0 00082ac3 _GPIO_EnableUnbondedIOPullups 0 00082ad9 _GPIO_ReadPin 0 00082af0 _GPIO_WritePin 0 00082b0e FS$$DIV 0 00082b96 _main 0 00082bdb _system_init 0 00082bec _sci_init 0 00082c11 _scib_TX 0 00082c1d _InitCpuTimers 0 00082c5e _ConfigCpuTimer 0 00082c99 _c_int00 0 00082cef C$$EXIT 0 00082cef _abort 0 00082cf1 _exit 0 00082d18 _InitPieCtrl 0 00082d37 _EnableInterrupts 0 00082d40 _InitPieVectTable 0 00082d66 _copy_in 0 00082d8a _memcpy 0 00082da7 __args_main 0 00082db9 _sciaRxFifoIsr 0 00082dc6 __register_unlock 0 00082dca __register_lock 0 00082dce __nop 0 00082dcf _SetDBGIER 0 00082dd2 __system_pre_init 0 00082dd4 __system_post_cinit 0 00086000 _RamfuncsLoadStart 0 00086072 _RamfuncsLoadEnd 0 00090000 _PieVectTableInit 1 00000400 __stack 1 00000500 __STACK_END 1 00000b00 _AdcaResultRegs 1 00000b20 _AdcbResultRegs 1 00000b40 _AdccResultRegs 1 00000b60 _AdcdResultRegs 1 00000c00 _CpuTimer0Regs 1 00000c08 _CpuTimer1Regs 1 00000c10 _CpuTimer2Regs 1 00000ce0 _PieCtrlRegs 1 00000d00 _EmuKey 1 00000d00 _PieVectTable 1 00000d01 _EmuBMode 1 00001000 _DmaRegs 1 00001400 _Cla1Regs 1 00004000 _EPwm1Regs 1 00004100 _EPwm2Regs 1 00004200 _EPwm3Regs 1 00004300 _EPwm4Regs 1 00004400 _EPwm5Regs 1 00004500 _EPwm6Regs 1 00004600 _EPwm7Regs 1 00004700 _EPwm8Regs 1 00004800 _EPwm9Regs 1 00004900 _EPwm10Regs 1 00004a00 _EPwm11Regs 1 00004b00 _EPwm12Regs 1 00005000 _ECap1Regs 1 00005020 _ECap2Regs 1 00005040 _ECap3Regs 1 00005060 _ECap4Regs 1 00005080 _ECap5Regs 1 000050a0 _ECap6Regs 1 00005100 _EQep1Regs 1 00005140 _EQep2Regs 1 00005180 _EQep3Regs 1 00005c00 _DacaRegs 1 00005c10 _DacbRegs 1 00005c20 _DaccRegs 1 00005c80 _Cmpss1Regs 1 00005ca0 _Cmpss2Regs 1 00005cc0 _Cmpss3Regs 1 00005ce0 _Cmpss4Regs 1 00005d00 _Cmpss5Regs 1 00005d20 _Cmpss6Regs 1 00005d40 _Cmpss7Regs 1 00005d60 _Cmpss8Regs 1 00005e00 _Sdfm1Regs 1 00005e80 _Sdfm2Regs 1 00006000 _McbspaRegs 1 00006040 _McbspbRegs 1 00006100 _SpiaRegs 1 00006110 _SpibRegs 1 00006120 _SpicRegs 1 00006200 _UppRegs 1 00007000 _WdRegs 1 00007060 _NmiIntruptRegs 1 00007070 _XintRegs 1 00007200 _SciaRegs 1 00007210 _ScibRegs 1 00007220 _ScicRegs 1 00007230 _ScidRegs 1 00007300 _I2caRegs 1 00007340 _I2cbRegs 1 00007400 _AdcaRegs 1 00007480 _AdcbRegs 1 00007500 _AdccRegs 1 00007580 _AdcdRegs 1 00007900 _InputXbarRegs 1 00007920 _XbarRegs 1 00007940 _SyncSocRegs 1 00007980 _DmaClaSrcSelRegs 1 00007a00 _EPwmXbarRegs 1 00007a80 _OutputXbarRegs 1 00007c00 _GpioCtrlRegs 1 00007f00 _GpioDataRegs 1 0000a800 _EPWM 1 0000a81a _CpuTimer0 1 0000a822 _CpuTimer1 1 0000a82a _CpuTimer2 1 0000a832 _ECAP 1 0000a840 _EQEP 1 0000a848 _SPI 1 0000a850 _tempSensor_tempSlope 1 0000a852 _tempSensor_tempOffset 1 0000a854 _tempSensor_scaleFactor 1 0000a856 _SDFM 1 0000a85c ___TI_enable_exit_profile_output 1 0000a85e ___TI_cleanup_ptr 1 0000a860 ___TI_dtors_ptr 1 0000a862 _I2C 1 0000a866 _MCBSP 1 0000a86a _SCI 1 0000a86e __lock 1 0000a870 __unlock 1 0000a872 _deviceOpen 1 0000a873 _a 1 00047000 _Emif1Regs 1 00047800 _Emif2Regs 1 00048000 _CanaRegs 1 0004a000 _CanbRegs 1 00050024 _FlashPumpSemaphoreRegs 1 0005d000 _DevCfgRegs 1 0005d180 _AnalogSubsysRegs 1 0005d200 _ClkCfgRegs 1 0005d300 _CpuSysRegs 1 0005e608 _RomPrefetchRegs 1 0005f000 _DcsmZ1Regs 1 0005f040 _DcsmZ2Regs 1 0005f070 _DcsmCommonRegs 1 0005f400 _MemCfgRegs 1 0005f480 _Emif1ConfigRegs 1 0005f4a0 _Emif2ConfigRegs 1 0005f4c0 _AccessProtectionRegs 1 0005f500 _MemoryErrorRegs 1 0005f540 _RomWaitStateRegs 1 0005f800 _Flash0CtrlRegs 1 0005fb00 _Flash0EccRegs 1 0005fc00 _Flash1CtrlRegs 1 0005ff00 _Flash1EccRegs 1 00078000 _DcsmZ1Otp 1 00078200 _DcsmZ2Otp abs 00000072 _RamfuncsLoadSize abs 00000072 _RamfuncsRunSize abs 00000100 __STACK_SIZE abs ffffffff .text abs ffffffff ___TI_pprof_out_hndl abs ffffffff ___TI_prof_data_size abs ffffffff ___TI_prof_data_start abs ffffffff ___binit__ abs ffffffff ___c_args__ abs ffffffff ___etext__ abs ffffffff ___pinit__ abs ffffffff ___text__ abs ffffffff binit abs ffffffff etext abs ffffffff pinit [351 symbols]
This is my .map file hope these information helps
Kindly help me out with this issue.
Hi,
I haven't changed the linker file, so by default, the code is placed in FLASH B, right?
In the future, do I always need to modify the linker file for the SCI bootloader to work, or is there a way to configure it correctly from the start?
As long as your application's codestart is at 0x0008 0000, then the application should be successfully booted to. You map file confirms this is case and the generic flash linker command file is setup to do that already, so no need to modify in the future.
I didn't know if this was the case because the linker command file snippets you provided omitted where the codestart was and only showed where the application was being loaded.
I tried this and its not working as required.
And when you say the application is not working, do mean when booting to flash on reset? Or after the serial_flash_programmer is finished programming the application.
Best,
Matt
Requirement:- Need to run application code after completion of commands through sci bootloader
And when you say the application is not working, do mean when booting to flash on reset? Or after the serial_flash_programmer is finished programming the application.
After all commands from Serial_flash_programmer is finished the application code fails to run. Only works when I switch to get mode and reset the mcu.
DO you need any other information for debugging?
Kindly provide solution to my issue.
Hi,
After all commands from Serial_flash_programmer is finished the application code fails to run. Only works when I switch to get mode and reset the mcu.
After you execute "1-DFU" in the serial_flash_programmer, do you do "6-Run" and specify the entry point of the application?
Best,
Matt
Hi matt,
Yes I use RUN command and specify the entry point
I have already mentioned the steps I performed in the discussion above. Could you please review the full conversation and address my issue accordingly?
Let me know if you need any specific details.
9.The application code got dumped and asked for next step ,I selected option 6 to run.
10.It then asked for the address to branch to.
11.I copied the entry point address from above and pasted it below.
Rajamurugan,
What address does the device branch to after receiving the run command? Does this only occur when branching to the application from the kernel, or also when booting from flash? Can you verify the contents of flash against your .out file using the C2000 Flash Utility "Verify Only" function?
Best,
Alex
Hi Matt,
Below, I've explained my issue for your clarification.
Setup: Initially, I changed the boot mode select pin using the on-chip flash tool in debug mode so that we could use the default SCI pins for the bootloader.
Issue: After completing the bootloader process, the RUN command executes successfully, but the application code does not run (it is not transitioning from the kernel to the application code).
What address does the device branch to after receiving the run command?
The Entry point address is 0x82c9a for code with FLASHA set
The Entry point address is 0x82d21 for code with FLASHB set
Does this only occur when branching to the application from the kernel, or also when booting from flash?
This issue occurs only when branching to application from kernel.
When booting from flash it's working good.
Can you verify the contents of flash against your .out file using the C2000 Flash Utility "Verify Only" function?
I can confirm that the code works as expected when booted from flash after a reset.
Could you please provide the steps to use the C2000 Flash Utility to verify with my .OUT file ?
Is there anything else I need to clarify? Please compile all necessary details in one response so I can work on them in a single day and get back to you quicker.
Thanks for assisting. I look forward to your response soon.