TMDSCNCD28379D: EPWM 4A not showing pulses

Hello,

I will take a look and reply in a timely manner.

Hello,

Have you done anything different while configuring EPW3 and EPWM4 for instance?

Hi Stevan

Here is the epwm settings:

void init_pwm(void)
{
EALLOW;

// Ref to page 108
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0x0; // such that oscclk takes from intosc2. intosc2 is 10MHz

ClkCfgRegs.SYSPLLMULT.bit.IMULT=0x28; // Pll CALCULATED FROM FORMULA IN PAGE 115 (SYS CONTROL)
ClkCfgRegs.SYSPLLMULT.bit.FMULT=0x00; // Pllsysclk is now at 400MHZ

ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; // to enable pll
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0x1; // TO RUN SYSCLOCK IN 200MHz. WHICH IS PLLSYSCLK
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 4; // Set initial divider at /8
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; // Switch over to use PLL output, 200 MHz /8 = 25 MHz
DelayUs(20/8);

ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 2; // Change to /4 divider
DelayUs(20/4); // Wait 20 us (just an example)

ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 1; // Change to /2 divider hence fpllclk = 200
DelayUs(20/4);

CpuSysRegs.PCLKCR2.bit.EPWM1=1; // TO ENABLE EPWM MODULE 1
CpuSysRegs.PCLKCR2.bit.EPWM2=1; // TO ENABLE EPWM MODULE 2
CpuSysRegs.PCLKCR2.bit.EPWM3=1; // TO ENABLE EPWM MODULE 2
CpuSysRegs.PCLKCR2.bit.EPWM4=1; // TO ENABLE EPWM MODULE 2
CpuSysRegs.PCLKCR2.bit.EPWM5=1;

ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; // Switch over to use PLL output

// SYS CLOCK running at 200 MHz
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1; // now EPWMclk is at 100 MHZ

// EPWM 1block
DevCfgRegs.SOFTPRES2.bit.EPWM1 = 1; // ePWM1 is reset
DevCfgRegs.SOFTPRES2.bit.EPWM1 = 0; // ePWM1 is released from reset
DevCfgRegs.CPUSEL0.bit.EPWM1=0; // Enable CPU1 to EPWM1
EPwm1Regs.TBCTL.bit.CTRMODE = 0x3; // Disable the timer
EPwm1Regs.TBCTL.all = 0xC533; // C533 means epwm is at 2khz. c4b3 means epwm is 4khz
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm1Regs.TBCTL.bit.PRDLD = 0;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0;
EPwm1Regs.TBCTL.bit.CLKDIV = 0x0; // This means TBCLK=EPWMCLK=100MHz
EPwm1Regs.TBCTR = 0x0000; // Clear timer counter
EPwm1Regs.TBPRD = 1999; // EPWM CLK at 50 kHz
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Set timer phase
EPwm1Regs.ETPS.all = 0x0000; // Configure interrupt at underflow of epwm1
EPwm1Regs.ETSEL.all = 0x0009; // Enable interrupt at underflow of epwm1
EPwm1Regs.ETSEL.bit.INTSEL = 1;
EPwm1Regs.ETSEL.bit.INTEN = 0;
EPwm1Regs.ETSEL.bit.INTSELCMP = 0;
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm1Regs.AQCTLA.bit.CAU = 1; // EPWM1A set to low on TBCTR=CMPA on up count
// EPwm1Regs.AQCTLA.bit.CAD = 0; // EPWM1A set to High on TBCTR=CMPA on down count
// EPwm1Regs.AQCTLB.bit.CBD = 0;
EPwm1Regs.AQCTLB.bit.CBU = 1;
EPwm1Regs.AQCTLA.bit.PRD = 2;
EPwm1Regs.DBCTL.bit.OUT_MODE = 0; // Deadband disabled, DB will be generated by the gate drivers
EPwm1Regs.TBCTL.bit.CTRMODE = 0x0; // Enable the timer in count up/down mode

//EPWM 2 block
DevCfgRegs.SOFTPRES2.bit.EPWM2 = 1; // ePWM1 is reset
DevCfgRegs.SOFTPRES2.bit.EPWM2 = 0; // ePWM1 is released from reset
DevCfgRegs.CPUSEL0.bit.EPWM2=0; // Enable CPU1 to EPWM1
EPwm2Regs.TBCTL.bit.CTRMODE = 0x3; // Disable the timer
EPwm2Regs.TBCTL.all = 0xC533; // C533 means epwm is at 2khz. c4b3 means epwm is 4khz
EPwm2Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm2Regs.TBCTL.bit.PRDLD = 0;
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0x0;
EPwm2Regs.TBCTL.bit.CLKDIV = 0x0;
EPwm2Regs.TBCTR = 0x0000; // Clear timer counter
EPwm2Regs.TBPRD = 1999; // EPWM CLK at 50 kHz
EPwm2Regs.TBCTL.bit.PHSDIR = 0; // EPWM
EPwm2Regs.TBCTL.bit.PHSEN = 1;
EPwm2Regs.TBPHS.bit.TBPHS = 400;
// EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Set timer phase
EPwm2Regs.ETPS.all = 0x0000; // Configure interrupt at underflow of epwm1
// EPwm2Regs.ETSEL.all = 0x0009; // Enable interrupt at underflow of epwm1
EPwm2Regs.ETSEL.bit.INTSEL = 1;
EPwm2Regs.ETSEL.bit.INTEN = 0;
EPwm2Regs.ETSEL.bit.INTSELCMP = 0;
EPwm2Regs.ETSEL.all = 0x0009;
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm2Regs.AQCTLA.bit.CAU = 1; // EPWM1A set to low on TBCTR=CMPA on up count
// EPwm2Regs.AQCTLA.bit.CAD = 2; // EPWM1A set to High on TBCTR=CMPA on down count
// EPwm2Regs.AQCTLB.bit.CBD = 2;
EPwm2Regs.AQCTLB.bit.CBU = 1;
EPwm2Regs.AQCTLA.bit.PRD = 2;
EPwm2Regs.DBCTL.bit.OUT_MODE = 0; // Deadband disabled, DB will be generated by the gate drivers
EPwm2Regs.TBCTL.bit.CTRMODE = 0x0; // Enable the timer in count up/down mode

//EPWM 3 block

DevCfgRegs.SOFTPRES2.bit.EPWM3 = 1; // ePWM1 is reset
DevCfgRegs.SOFTPRES2.bit.EPWM3 = 0; // ePWM1 is released from reset
DevCfgRegs.CPUSEL0.bit.EPWM3=0; // Enable CPU1 to EPWM1
EPwm3Regs.TBCTL.bit.CTRMODE = 0x3; // Disable the timer
EPwm3Regs.TBCTL.all = 0xC533; // C533 means epwm is at 2khz. c4b3 means epwm is 4khz
EPwm3Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm3Regs.TBCTL.bit.PRDLD = 0;
EPwm3Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0x0;
EPwm3Regs.TBCTL.bit.CLKDIV = 0x0;
EPwm3Regs.TBCTR = 0x0000; // Clear timer counter
EPwm3Regs.TBPRD = 1999; // EPWM CLK at 50 kHz
EPwm3Regs.TBCTL.bit.PHSDIR = 0; // EPWM
EPwm3Regs.TBCTL.bit.PHSEN = 1;
EPwm3Regs.TBPHS.bit.TBPHS = 800;
// EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Set timer phase
EPwm3Regs.ETPS.all = 0x0000; // Configure interrupt at underflow of epwm1
// EPwm3Regs.ETSEL.all = 0x0009; // Enable interrupt at underflow of epwm1
EPwm3Regs.ETSEL.bit.INTSEL = 1;
EPwm3Regs.ETSEL.bit.INTEN = 0;
EPwm3Regs.ETSEL.bit.INTSELCMP = 0;
// EPwm3Regs.ETSEL.all = 0x0009;
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm3Regs.AQCTLA.bit.CAU = 1; // EPWM1A set to low on TBCTR=CMPA on up count
// EPwm2Regs.AQCTLA.bit.CAD = 2; // EPWM1A set to High on TBCTR=CMPA on down count
// EPwm2Regs.AQCTLB.bit.CBD = 2;
EPwm3Regs.AQCTLB.bit.CBU = 1;
EPwm3Regs.AQCTLA.bit.PRD = 2;
EPwm3Regs.DBCTL.bit.OUT_MODE = 0; // Deadband disabled, DB will be generated by the gate drivers
EPwm3Regs.TBCTL.bit.CTRMODE = 0x0; // Enable the timer in count up/down mode

//EPWM 4 block

// to operate EPWM4A, pull up needs to be disabled

DevCfgRegs.SOFTPRES2.bit.EPWM4 = 1; // ePWM1 is reset
DevCfgRegs.SOFTPRES2.bit.EPWM4 = 0; // ePWM1 is released from reset
DevCfgRegs.CPUSEL0.bit.EPWM4=0; // Enable CPU1 to EPWM1
EPwm4Regs.TBCTL.bit.CTRMODE = 0x3; // Disable the timer
EPwm4Regs.TBCTL.all = 0xC533; // C533 means epwm is at 2khz. c4b3 means epwm is 4khz
EPwm4Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm4Regs.TBCTL.bit.PRDLD = 0;
EPwm4Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x0;
EPwm4Regs.TBCTL.bit.CLKDIV = 0x0;
EPwm4Regs.TBCTR = 0x0000; // Clear timer counter
EPwm4Regs.TBPRD = 1999; // EPWM CLK at 50 kHz
EPwm4Regs.TBCTL.bit.PHSDIR = 0; // EPWM
EPwm4Regs.TBCTL.bit.PHSEN = 1;
EPwm4Regs.TBPHS.bit.TBPHS = 1200;
// EPwm4Regs.TBPHS.bit.TBPHS = 0x0000; // Set timer phase
EPwm4Regs.ETPS.all = 0x0000; // Configure interrupt at underflow of epwm1
// EPwm4Regs.ETSEL.all = 0x0009; // Enable interrupt at underflow of epwm1
EPwm4Regs.ETSEL.bit.INTSEL = 1;
EPwm4Regs.ETSEL.bit.INTEN = 0;
EPwm4Regs.ETSEL.bit.INTSELCMP = 0;
// EPwm4Regs.ETSEL.all = 0x0009;
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm4Regs.AQCTLA.bit.CAU = 2; // EPWM1A set to low on TBCTR=CMPA on up count
EPwm4Regs.AQCTLA.bit.CAD = 2; // EPWM1A set to High on TBCTR=CMPA on down count
EPwm4Regs.AQCTLB.bit.CBD = 2;
EPwm4Regs.AQCTLB.bit.CBU = 2;
EPwm4Regs.AQCTLA.bit.PRD = 2;
EPwm4Regs.AQCTLA.bit.ZRO = 2;
EPwm4Regs.DBCTL.bit.OUT_MODE = 0; // Deadband disabled, DB will be generated by the gate drivers
EPwm4Regs.TBCTL.bit.CTRMODE = 0x0; // Enable the timer in count up/down mode

//EPWM 5 Block
// to operate EPWM4A, pull up needs to be disabled
DevCfgRegs.SOFTPRES2.bit.EPWM5 = 1; // ePWM1 is reset
DevCfgRegs.SOFTPRES2.bit.EPWM5 = 0; // ePWM1 is released from reset
DevCfgRegs.CPUSEL0.bit.EPWM5=0; // Enable CPU1 to EPWM1
EPwm5Regs.TBCTL.bit.CTRMODE = 0x3; // Disable the timer
EPwm5Regs.TBCTL.all = 0xC533; // C533 means epwm is at 2khz. c4b3 means epwm is 4khz
EPwm5Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm5Regs.TBCTL.bit.PRDLD = 0;
EPwm5Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0x0;
EPwm5Regs.TBCTL.bit.CLKDIV = 0x0;
EPwm5Regs.TBCTR = 0x0000; // Clear timer counter
EPwm5Regs.TBPRD = 1999; // EPWM CLK at 50 kHz
// EPwm5Regs.TBCTL.bit.PHSDIR = 0; // EPWM
EPwm5Regs.TBCTL.bit.PHSEN = 1;
EPwm5Regs.TBPHS.bit.TBPHS = 0;
// EPwm5Regs.TBPHS.bit.TBPHS = 0x0000; // Set timer phase
EPwm5Regs.ETPS.all = 0x0000; // Configure interrupt at underflow of epwm1
// EPwm5Regs.ETSEL.all = 0x0009; // Enable interrupt at underflow of epwm1
EPwm5Regs.ETSEL.bit.INTSEL = 1;
EPwm5Regs.ETSEL.bit.INTEN = 0;
EPwm5Regs.ETSEL.bit.INTSELCMP = 0;
// EPwm4Regs.ETSEL.all = 0x0009;
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
//test 25/11 EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0; // shadow A mode disabled
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm5Regs.AQCTLA.bit.CAU = 2; // EPWM1A set to low on TBCTR=CMPA on up count
EPwm5Regs.AQCTLA.bit.CAD = 2; // EPWM1A set to High on TBCTR=CMPA on down count
EPwm5Regs.AQCTLB.bit.CBD = 2;
EPwm5Regs.AQCTLB.bit.CBU = 2;
EPwm5Regs.AQCTLA.bit.PRD = 2;
EPwm5Regs.AQCTLA.bit.ZRO = 2;
EPwm5Regs.DBCTL.bit.OUT_MODE = 0; // Deadband disabled, DB will be generated by the gate drivers
EPwm5Regs.TBCTL.bit.CTRMODE = 0x0; // Enable the timer in count up/down mode

PieVectTable.EPWM1_INT = &phA_0;
IER |= M_INT3; // means enter third group of Interrupts Page 95
IER |= M_INT1;
PieCtrlRegs.PIEIER3.bit.INTx1=1; // interrupt 3.1= epwm 1 INT page 95

PieVectTable.EPWM2_INT = &phB_0;
IER |= M_INT3; // means enter third group of Interrupts Page 95
IER |= M_INT2;
PieCtrlRegs.PIEIER3.bit.INTx2=1; // interrupt 3.1= epwm 1 INT page 95

PieVectTable.EPWM3_INT = &phC_0;
// IER |= M_INT3; // means enter third group of Interrupts Page 95
// IER |= M_INT3;
// PieCtrlRegs.PIEIER3.bit.INTx3=1; // interrupt 3.1= epwm 1 INT page 95

CpuSysRegs.PCLKCR2.bit.EPWM3=1; // TO ENABLE EPWM MODULE 2
CpuSysRegs.PCLKCR2.bit.EPWM4=1; // TO ENABLE EPWM MODULE 2
CpuSysRegs.PCLKCR2.bit.EPWM5=1; // TO ENABLE EPWM MODULE 2

// PieVectTable.TIMER1_INT = &timer1_intsr;

// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
asm(" EALLOW"); // Enable EALLOW protected register access
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // TBCLK to ePWM modules enabled
EDIS;

// Enable CPU INT3 which is connected to EPWM1-3 INT:
// IER |= M_INT13;

}

For GPIOs, I have:

GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 0; // 0|0=GPIO 0|1=EPWM1A 0|2=rsvd 0|3=rsvd
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // 1|0=GPIO 1|1=rsvd 1|2=SDAA 1|3=rsvd
GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 0; // 0|0=GPIO 0|1=EPWM1B 0|2=rsvd 0|3=MFSRB
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1;

GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0; // 0|0=GPIO 0|1=EPWM1B 0|2=rsvd 0|3=MFSRB
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0; // 0|0=GPIO 0|1=EPWM1B 0|2=rsvd 0|3=MFSRB
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO3 = 1;

GpioCtrlRegs.GPAGMUX1.bit.GPIO4 = 0; // 0|0=GPIO 0|1=EPWM1B 0|2=rsvd 0|3=MFSRB
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO5 = 0; // 0|0=GPIO 0|1=EPWM1B 0|2=rsvd 0|3=MFSRB
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 0; // 0|0=GPIO 0|1=EPWM1B 0|2=rsvd 0|3=MFSRB
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO4 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO5 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A)
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A)

GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO7 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1;

Regards

Rupak

6281.MPB.zip