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TMS320F280039C: ADC interrupt overflow issue

Strong ZHANG
Expert 4300 points
Part Number: TMS320F280039C

Tool/software:

Hi Expert,

My customer are EPWM1 zero event to trigger SOC, and generate ADC interrupt,  the pwm and interrupt frequency is 20Khz.

they face have issue that their interrupt time may exceed the 50us, which is overflow, they do below test to reproduce the issue:

in above interrupt code, at 65th line, if they use RPT function over 200 times, then the adc interrupt will not occur,

but if they use RPT function equal 199 times, the adc interrupt will become 10KHz.

The have a gpio toggle in the interrupt and they capture the waveform below when overflow happen,

they find that the interrupt frequency become 10Khz.

question is why the interrupt frequency will change when RPT function equal 199 times? 

  • 0
    TI__Intellectual 820 points

    Hi Strong,

    I am suspecting that the interrupt is not getting cleared properly.

    Assuming the CPU is running at 100MHz the total wait time is about 57.6uS >50us for the 24 lines of RPT this will result in overflow, can you chek if the overflow flag is being set ?

    Currently not able to get why 199 will work and give half the frequency (This indicates that alternate conversions are being read in ISR). 

    BR,

    Nilesh

  • 0 in reply to Nilesh Khanna
    TI__Expert 4300 points

    Nilesh，

    customer are using F280039 with 120MHz. could you help specify what overflow flag is being set?

  • 0 in reply to Strong ZHANG
    TI__Intellectual 820 points

    Hi Strong,

    Above is the table for the Oveflow Interupt flags based on the ADC interrupt chosen in the code. The flag can be monitored while using tha above example to reproduce the issue.

    Thanks,

    Nilesh

  • 0 in reply to Nilesh Khanna
    TI__Expert 4300 points

    Nilesh,

    Yes the adc flag was set when they use 199 and give half the frequency, anything further explanation? 

  • 0 in reply to Strong ZHANG
    TI__Intellectual 820 points

    Hi Strong,

    Esentially it means that the ADC interrupt is not being cleared before the next ADC relsult is triggered.

    The time with 120Mhz will also be 48us(Calculated) + 1.65us(199 from line 65) ~= to 50us (If statment will also take some cycle to evaluate so total time will again exceed sampling time)

    We can clear the overflow Flag as well after the interrupt is cleared. But we will miss some samples here, if we are okay to miss the sample then clearing overflow flag should resolve the issue. 

    Thanks,

    Nilesh