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SPI - Problem with 28035 and DAC8555

Adel
Prodigy 135 points
Other Parts Discussed in Thread: DAC8555

Hello

I'm working with a 28035 mcu  and trying to set up the spi interface to work with DAC8555

It runs at 1 Mhz.  It has 3 pins - DO (dataout), SYNC and CLK (clock).

 I've set the 28035 up as follows:

28035 is master, character size is 12  bits.and the Dac8555 Data is clocked into the 24-bit input.

 the master loaded the data  into TX buffer and the transmit as follows:

 SpiaRegs.SPITXBUF = (Value_To_Register & 0x00FFF000) >> 8;

SpiaRegs.SPITXBUF = (Value_To_Register & 0x00000FFF) << 4;

and the DAC8555 is Updated .

the problem happened if an interrupt occured ( i have adealy between the two Transmitted instructions)  the Sync signal rise one clock time and Fall back, and the data not transmit correctly and the DAC doesn't updated.

i try to stop the by SPI SW RESET Bit and enable afeter loaded the tx  fifo as follows:

 SpiaRegs.SPICCR.bit.SPISWRESET = 0;
 SpiaRegs.SPITXBUF = (Value_To_Register & 0x00FFF000) >> 8;

SpiaRegs.SPITXBUF = (Value_To_Register & 0x00000FFF) << 4;

 SpiaRegs.SPICCR.bit.SPISWRESET = 1;

but the tx fifo buffer  reset and no data transmittrd.

Can anyone help me how can i ensure transmitting the data , whether i have adealy between the data transmit?

Regards

Adel

 

 

 

 

 

 

 

 

 

 

  • 0
    Expert 1235 points

    Adel,

    Why "sync" pulse on an interrupt? You should prevent the "sync" signal corruption in the interrupt routine if the SPI is busy Xmiting.

    "SpiaRegs.SPICCR.bit.SPISWRESET = 1;

    but the tx fifo buffer  reset and no data transmittrd."

    Is what the reset suppose to do.

  • 0 in reply to Joe Josn
    Intellectual 300 points

    Hallo,

    I have just the same issue..

    the question is how can I load a couple of words into the FIFO and XMIT only after these words are loaded ?

    this means that the first loading of the SPITXBUF will NOT generate a XMIT session.

    obviously, the problem is that if an interrupt occurs between the loading of the FIFO, then the SPI will XMIT the words that are in the FIFO (pulling SYNC to low and provide clock), but then it will stop XMIT (no more words in the FIFO), jump to the interrupt (and pull the SYNC high, stop clock) , come back and will then resume filling the FIFO and XMIT..

    this will cause the slave on the SPI not to understand correctly the whole message.

    example:

    SPITXBUF = value;

    SPITXBUF = value;

    --->> jump to an interrupt

    SPITXBUF = value;

    SPITXBUF = value;

     

    this will cause the 4 words loaded not to be transmitted properly (of course eventually they would all be XMITed) - and the slave will not understand.

     

    one solution to this problem is to load the FIFO in an interrupt (assuming nested interrupts is not used) - so there will be no interruptions...

    but how can I do it outside an interrupt ?

    I tried using all sorts of bits in the registers (all kind of RST options, TALK bit, Enable bit etc). none of them worked correctly.

     

    thanks a lot

    Ari.

  • 0 in reply to Aristafari
    Expert 1235 points

    Ari,

    Assuming that you are using SPI TXFIFO (16 words) you should 1) Disable interrupts, 2) Load all your values to TXFIFO (up to 16 words) and then 3) Enable Interrupts. The disable()/enable() will prevent any interruptions during loading of TXFIFO.

    OR

    Control the SYNC pulse by your logic to guarantee all data bits are clocked out before SYNC goes back high.