TMS320F28P650DK: CCS Theia error: CPU2 flash banks locked and not configurable - solution often fails

Stewart Innes

Part Number: TMS320F28P650DK

This is related to the discussion here: question

and here:
[FAQ]

Following the solution from the FAQ sometimes works, but not always. It appears that something gets "stuck" after repeated flashing or debug sessions. It never works when you allow the GUI Composer to flash the device, and then the FAQ solution also stops working for some time.

Following the FAQ solution from a clean power-up:

Start project-less debug from TMS320F28P650DK9.ccxml (created from example project)
Connect to both cores
Properties>CPU1>Flash settings > configure bank 0-2 for CPU1 and 3-4 for CPU2
Erase settings: only erase bank 0-2
Configure clock
Save and close
Continue CPU1
Load>(my program, an example program, it doesn't seem to matter)
Properties>CPU2> Note that the flash bank map settings are greyed out and all are set to 0
Erase settings: only erase banks 3 and 4
Save and close
Continue CPU2
Run>Load> my program
Success

Try to open a GUI Composer program, and realize that it tried to flash the program again (despite `symbolsOnly=true` in the gc-model-program) and failed:

So we try the previous steps again

Start debugging
Connect both cores
Check configuration is still good
Configure clock
Run, then load CPU1
Check CPU2 configuartion
Run, then load CPU2
Fail:

Power cycle, try again, it still fails. Eventually I can try to flash and reflash and get it to work, but it's about 1 in 10 attempts.

A couple of things I've noticed that could be clues:

When I flash CPU1, the popup in the bottom right corner will say something to the effect of "Erasing Bank 0", then "Erasing Bank 1", then 2 and then also 3 briefly before continuing on - despite bank 3 being configured for CPU2 and not checked to be erased with CPU1
If I do a "Blank Check" in the error state, this is the message: C28xx_CPU2: Flash Programmer: Error during Blank Check @ address 0x00080000; expected 0xFFFFFFFF, actual 0x00000000 (0).
Does that suggest that the "erase" function is filling with 0 instead of F? Is that a configuration option?

5 days ago

0 Peter Luong1 3 days ago

TI__Mastermind 18531 points

Hi Stewart,

Is this a custom GUI Composer program or one that is available on the Gallery. I'm trying to determine if it's possible the GUI Composer application could be causing some issue. Are you leveraging the program loader component or another approach to flashing the device. Let me also see feedback from the engineer who was assisting with the referenced thread

Regards,

Peter

0 Stewart Innes 3 days ago in reply to Peter Luong1

Prodigy 20 points

It is a custom GUI Composer program, but it's the simplest possible one, made by following the linked thread exactly. I think there are two problems:

1. The default mechanism for flashing a dual-core microcontroller does not work, so I need to do the debug-mode workaround. As others have pointed out, this is a very slow development workflow. In my case, it appears to not always work.

2. The GUI Composer v3 method for interacting with two cores does not respect the `symbolsOnly` flag in `gc-model-program`, so it insists on flashing the device, undoing the workaround from problem 1.

Here's the only changes I made to the default v3 project (besides uploading my .out files to ./firmware)


<gc-target-connection-manager id="connection_manager" auto-connect active-configuration="xds_1(pm_1,pm_2)">
<gc-transport-xds id="xds_1" device-name="TMS320F28P650DK9" connection-name="Texas Instruments XDS110 USB Debug Probe"></gc-transport-xds>
<gc-model-program id="pm_1" core-name="C28xx_CPU1" program-or-bin-path="./firmware/cpu1.out" symbolsOnly optional></gc-model-program>
<gc-model-program id="pm_2" core-name="C28xx_CPU2" program-or-bin-path="./firmware/cpu2.out" symbolsOnly optional></gc-model-program>
</gc-target-connection-manager>

I tried setting `symbolsOnly="true"` and a few other variations as well. Same with including/excluding the `optional` flag.

0 Charles Roberson 3 days ago

TI__Genius 14740 points

Hi Stewart,

>1. When I flash CPU1, the popup in the bottom right corner will say something to the effect of "Erasing Bank 0", then "Erasing Bank 1", then 2 and then also 3 briefly before continuing on - despite bank 3 being configured for CPU2 and not checked to be erased with CPU1

Can you state the CCS Theia version that is providing these statements? Is this with the latest version of CCS Theia?

>2. If I do a "Blank Check" in the error state, this is the message: C28xx_CPU2: Flash Programmer: Error during Blank Check @ address 0x00080000; expected 0xFFFFFFFF, actual 0x00000000 (0).
Does that suggest that the "erase" function is filling with 0 instead of F? Is that a configuration option?

This suggests that CPU2 does not have ownership of Flash Bank 3 (0x0000 values seen in CPU2 Flash Memory window view). Can you provide confirmation of the memory window for CPU2 at Flash Bank 3 address, as well as the current Flash Bank owners through BankMuxSel in register view?

Thanks and regards,

Charles