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LAUNCHXL-F29H85X: Spread Spectrum Frequency Modulation

Jan Bock
Expert 3630 points

Part Number: LAUNCHXL-F29H85X

 I've with testing and have a few questions here. (The LaunchXL could be a bit more friendly for external debuggers , but everything has worked well so far) regarding ePWM:

  • One requirement on our side is Spread Spectrum Frequency Modulation => varying the output PWMs in frequency to minimize EMI.

Apart from changing the period for all ePWMs simultaneously, I haven't seen any way to implement this on the C29. Since I don't have much experience with the C2000, this causes me some concern, partly because we're using a dual active bridge where the phase between 2 PWMs reacts very sensitively and is constantly regulated. Have you implemented something like this before? Also because a pure software implementation negatively affects performance (cyclically changing 24 PWM periods, calculating new control parameters and new phase offsets)

Comparing C28 and C29: the C29 no longer has a CLA, is there a similar hardware accelerator to post-process/filter ADC data, for example? Or can the CLB be used for this?

 

  • +1
    TI__Mastermind 27736 points

    Hi Jan,

    Jan Bock said:
    Apart from changing the period for all ePWMs simultaneously, I haven't seen any way to implement this on the C29. Since I don't have much experience with the C2000, this causes me some concern, partly because we're using a dual active bridge where the phase between 2 PWMs reacts very sensitively and is constantly regulated. Have you implemented something like this before? Also because a pure software implementation negatively affects performance (cyclically changing 24 PWM periods, calculating new control parameters and new phase offsets)

    There is a way to change any of the registers between all PWM bases using the DEVCFG.EPWMXLINKCFG register configuration. Here is a FAQ in this.

    1.  [FAQ] F29x ePWM: Frequently Asked Questions 
      1. Go to "In the TRM, why is the description of EPWMXLINK missing?"

    Best regards,

    Ryan Ma

  • 0 in reply to Ryan Ma
    TI__Expert 3630 points

    Thank you for the feedback. Yes, xlink could be used for the PWM duty cycles. The frequency change is probably easier if you keep all PWMs as slave PWMs in freerunning mode and set the frequency via the Master.

    I have another question regarding interrupt performance. My setup:

    • ADC with repeat active (50MHz, 6 ACQPS, n channels with m repeats)
    • Trigger of the repeater via ePWM1
    • RTDMA trigger via ADCA interrupt

    1. Due to the memory architecture in the ADC, you have to read all 16 result registers via DMA, otherwise you lose data. Can you confirm this?

    2. With n=8 channels, I can execute all possible repeats and they are triggered and executed correctly. However, if I only sample n=2 channels, the number of repeats varies (e.g., with m=5 and n=2, it only samples once).

    • Is there a timing issue with the interrupts? If so, what is their maximum resolution? If there's another reason, please correct me. I've tested this with pin toggles in the interrupts, as I'm just setting up the eRAD module.

    c) Can the interrupt latency be bypassed and the DMA be triggered without interrupts? d) The PPBs would also be interesting, but if I've seen correctly, there are only 4 PPBs per ADC (with clever allocation, this might be sufficient)

  • 0 in reply to Jan Bock
    TI__Mastermind 27736 points

    Hi Jan,

    Could you create a separate e2e threads on the following questions so we can route this to the correct subject matter experts?

    Jan Bock said:

    1. With n=8 channels, I can execute all possible repeats and they are triggered and executed correctly. However, if I only sample n=2 channels, the number of repeats varies (e.g., with m=5 and n=2, it only samples once).

    • Is there a timing issue with the interrupts? If so, what is their maximum resolution? If there's another reason, please correct me. I've tested this with pin toggles in the interrupts, as I'm just setting up the eRAD module.

    This will need to go to our ADC expert. Please create a separate thread for this one. 

    I can help answer these queries. If these help answer your questions please mark this thread as resolved and I can help get the above thread assigned to someone on our team.

    Jan Bock said:

    • Due to the memory architecture in the ADC, you have to read all 16 result registers via DMA, otherwise you lose data. Can you confirm this?

    That is correct, before the next start of conversion completes if data has not been read from the ADC Result registers, they will be overwritten with the new ADC result values.

    Jan Bock said:
    c) Can the interrupt latency be bypassed and the DMA be triggered without interrupts? d) The PPBs would also be interesting, but if I've seen correctly, there are only 4 PPBs per ADC (with clever allocation, this might be sufficient)

    Yes DMA has trigger sources from the ADC that you could leverage. There are only 4 PPBs that is correct.

    Best regards,

    Ryan Ma

  • 0 in reply to Ryan Ma
    TI__Expert 3630 points
    Ryan Ma said:

    This will need to go to our ADC expert. Please create a separate thread for this one. 

    I can help answer these queries. If these help answer your questions please mark this thread as resolved and I can help get the above thread assigned to someone on our team.

    e2e.ti.com/.../launchxl-f29h85x-interrupt-performance-adc-readings

  • 0 in reply to Jan Bock
    TI__Mastermind 27736 points

    Hi Jan,

    Looks like this thread has been assigned, hope your question can be answered by today.

    Best regards,

    Ryan Ma