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TMS320C6655: Access bit width restriction issue when using DDR ECC function on TMS32C6655 processor

Bin Zhou
Prodigy 10 points
Part Number: TMS320C6655


Referring to the official development board C6655 processor, there are three DDR chips attached, two of which are used for data caching and the third for ECC verification.

When in use, DDR access can only be in 64 bit mode, and the address must be strictly aligned with 8 bytes, otherwise ECC checksum errors will be reported.

We have many scenarios for 16 bit data access. May I ask how to modify this configuration to enable ECC support for 16 bit access mode

  • 0
    TI__Expert 5150 points

    Hi,

    Please refer: Keystone Architecture DDR3 Memory Controller.

    ECC protected writes must be performed to a 64-bit aligned address with a byte count that is a multiple of 64-bits. If these alignment or quanta conditions are not met, a write ECC error may be generated.

    Link from the previous E2E post :https://e2e.ti.com/support/processors-group/processors/f/processors-forum/756278/tms320c6678-ecc-error-when-performing-wbinv?

    Bin Zhou said:
    We have many scenarios for 16 bit data access. May I ask how to modify this configuration to enable ECC support for 16 bit access mode

    I will check this internally and let you know.

    Regards,

    Betsy Varughese

  • 0 in reply to Betsy Varughese
    TI__Expert 5150 points

    Hi,

    Apologies for the delay.

    Please expect a response early next week, as most of our team is on vacation. I’ve also looped in our hardware expert for additional input.

    Regards,
    Betsy Varughese
  • 0 in reply to Betsy Varughese
    TI__Guru 55367 points

    Hi,

    If you are performing direct CPU writes to SDRAM memory space that is not cached, or using DMA or any other initiator to write to SDRAM then the 64b aligned/64b long rules must be followed for ECC to be calculated.  

    If the memory space is cached and the CPU is performing 16b writes then the cache will help to respect the 64b aligned/long rule.  

    The underlying issue is that the ECC is calculated on 64b data.  So if you're modifying only part of the existing 64b data then the EMIF controller doesn't have the necessary info to recalculate the ECC using the new and pre-existing data.

    Regards,

    Kyle

  • 0 in reply to kcastille
    TI__Mastermind 29682 points

    Thanks Kyle,

    kcastille said:
    So if you're modifying only part of the existing 64b data then the EMIF controller doesn't have the necessary info to recalculate the ECC using the new and pre-existing data.

    The operation between cache and EMIF should be cache line sized aligned, which is 128byte(or 256byte?) aligned, multiple of 64byte, does it still have the underlying issue?

  • 0 in reply to Tony Tang
    TI__Expert 5150 points

    Hi Tony Tang,

    Are the 16-bit writes being performed by the CPU through cache, or are there any direct (uncached) CPU writes or DMA/peripheral writes to the same DDR region?

    Regards,

    Betsy Varughese

  • 0 in reply to Betsy Varughese
    Prodigy 10 points

    Thanks Betsy Varughese,

    The 16-bit writes being performed by  direct (uncached) CPU writes.

    The data source comes from the CPU or SRIO peripherals. As the SRIO bus is accessed with 64 bits, can the data from SRIO be directly mapped to DDR through DMA, with ECC verification enabled for this part？  Can ECC verification be disabled for the other part that is directly accessed through the CPU?

  • 0 in reply to Bin Zhou
    TI__Expert 5150 points

    Hi Bin Zhou,

    Bin Zhou said:
    The 16-bit writes being performed by  direct (uncached) CPU writes.

    As mentioned earlier, then the 64b aligned/64b long rules must be followed for ECC to be calculated.  

    Bin Zhou said:
    The data source comes from the CPU or SRIO peripherals. As the SRIO bus is accessed with 64 bits, can the data from SRIO be directly mapped to DDR through DMA, with ECC verification enabled for this part？  Can ECC verification be disabled for the other part that is directly accessed through the CPU?

    No, ECC cannot be selectively disabled for only part of DDR that is directly accessed by the CPU. ECC enable/disable applies to the entire DDR/EMIF space.

    Regards,

    Betsy Varughese

  • 0 in reply to Betsy Varughese
    TI__Guru 55367 points

    Hi Bin, Betsy,

    Bin Zhou said:
    The data source comes from the CPU or SRIO peripherals. As the SRIO bus is accessed with 64 bits, can the data from SRIO be directly mapped to DDR through DMA, with ECC verification enabled for this part？  Can ECC verification be disabled for the other part that is directly accessed through the CPU?
    I don't think Betsy's answer is correct based on my interpretation of the Keystone Architecture DDR3 Memory Controller appnote.  Refer to the registers ECCCTL, ECCADDR1 and ECCADDR2.
    Regards,
    Kyle
  • 0 in reply to kcastille
    TI__Expert 5150 points

    Hi Kyle, Bin,

    Apologies for the confusion in my earlier response. After revisiting the Keystone Architecture DDR3 Memory Controller application note, I see that your interpretation is correct. Thanks for highlighting this.

    The eight-bit ECC is calculated over 64-bit data quanta. ECC is enabled by setting ECC_EN = 1 in the ECC Control register. ECC is disabled by setting ECC_EN=0. By default, ECC_EN=0. The address ranges can be programmed in the ECC Address Range 1 (section 4.28: ECCADDR1) and 2 (section 4.29: ECCADDR2) register. (section 2.17).

    Regards,

    Betsy Varughese