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Implementing algorithms on CLA (F28069)

Hi,

I am currently evaluating the piccolo DSC and I would like to implement a first algo that uses the capabilities of the CLA. Particularly, I want to implement a bank of filters, that operate sample-wise on the adc output.

My questions are as follows:

- assume that the sampling frequency at the adc is 100kHz, and that the processor is operating at 80MHz. Theoreticaly, between 2 samples there are 800 core cycles that can be used for calculations. Is there any overhead or delay due to the interrupt or something else that decreases this 800cycles, and if so how much?

- how can I test my implementation without an evaluation board (still waiting for it)? Does the CCS contain a simulator, that can simulate the CLA architecture?

Bye,

Nedzad

  • Hi Nedzad

    Nedzad Siljak said:

    - assume that the sampling frequency at the adc is 100kHz, and that the processor is operating at 80MHz. Theoreticaly, between 2 samples there are 800 core cycles that can be used for calculations. Is there any overhead or delay due to the interrupt or something else that decreases this 800cycles, and if so how much?

    There is an early ADC triggering mechanism whereby you setup the adc to trigger a task at the start-of-conversion. Lets say we do this for task 1 -- the ADC will trigger task 1 when it starts converting(takes 15 cycles to convert), it takes 7 cycles to get into task 1 leaving you with an additional 8 cycles to do some precalculations or moves before the ADC result is ready. With this mechanism there is no latency between sampling to control ---  the Tech Reference manual for your particular device will give more details on this option

    Nedzad Siljak said:
    - how can I test my implementation without an evaluation board (still waiting for it)? Does the CCS contain a simulator, that can simulate the CLA architecture?

    I was going through the simulator options in CCS and it doesnt look like the CLA is supported.