Hi,
I am currently evaluating the piccolo DSC and I would like to implement a first algo that uses the capabilities of the CLA. Particularly, I want to implement a bank of filters, that operate sample-wise on the adc output.
My questions are as follows:
- assume that the sampling frequency at the adc is 100kHz, and that the processor is operating at 80MHz. Theoreticaly, between 2 samples there are 800 core cycles that can be used for calculations. Is there any overhead or delay due to the interrupt or something else that decreases this 800cycles, and if so how much?
- how can I test my implementation without an evaluation board (still waiting for it)? Does the CCS contain a simulator, that can simulate the CLA architecture?
Bye,
Nedzad