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F28069 CLA RAM access

Cyril Lance
Intellectual 270 points

Hi there.

I am using a Picollo F28069 and using the CLA RAM with both CPU and CLA access set at the same time which the datasheet says it's OK.

I initialize the bits as:

Cla1Regs.MMEMCFG.bit.PROGE = 1;

Cla1Regs.MMEMCFG.bit.RAM0E = 1;

Cla1Regs.MMEMCFG.bit.RAM0CPUE = 1;        // Allow CPU access to ClaDataRam
Cla1Regs.MMEMCFG.bit.RAM1E = 1;

Cla1Regs.MMEMCFG.bit.RAM1CPUE = 1;       // Allow CPU access to ClaDataRam

Somehow when the program is running, the CPU can no longer access the CLA RAM unless I call (again)

EALLOW;

Cla1Regs.MMEMCFG.bit.RAM0CPUE = 1;

EDIS;

before trying to access the CLA RAM.

We cannot examine the registers in the debugger (I think CCS does not yet have an updated gel file for this?) so I can't see if somehow this bit is being reset to 0, but I know my code is not setting it explicitly.

Has anyone else had trouble with this?

Thanks,

Cyril

 

 

  • 0
    Intellectual 545 points

    Hi Cyril,

    according to table 9-4 of SPRUH18 you must set to 0 the RAMxCPUE bits in order to always allow CPU to access to CLA data memory.

    Regards,

    Raffaele

  • 0 in reply to Raffaele
    Intellectual 270 points

    Hi Raffaele,

    Thanks for the note.  In that table, I read it as if

    RAMxE = 1  and RAMxCPUE = 1 then CPU data access is allowed to CLA RAM (as well as CLA access to the RAM).

    This is the mode I'm trying to run it in.  TI has told me this is valid, but it only works if I repeatedly reset the RAMxCPUE bit to 1 just before my READ to the RAM.  Puzzling....

    I can examine the PROGE, RAM0E and RAM1E bits in the debugger, but the RAMXCPUE bits are not available (yet) so I cannot see if or when those bits are being reset.

    Cyril

  • 0 in reply to Cyril Lance
    TI__Mastermind 43730 points

    Please see

    http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/p/218230/770892.aspx#770892

    this is part of the errata,