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problems with reading/writing from/to RAM/XINTF zone with 32 bit data transfer

I am using eZDSP with an 28355 DSC and tried to change the provided example "Example_2833xDMA_xintf_to_ram" from using 16 bit data transfer to using 32 bit data transfer. However, if I configure register XTIMING7.bit.XSIZE = 1, then neither DMA transfer of a 32Bit data (DMA configured for 32 bit transfer: DMA MODE.bit.DATASIZE=1 and BURST_SIZE.all = 1) nor access to zone 7 directly sets the high 16 bit of the data correctly.

Example:

#pragma DATA_SECTION(foo,"ZONE7DATA");

volatile Uint32 foo;  // adress of this variable is even ( 0x0020FC00 )

 

void main(void)

{

    init_zone7();    // initialisation of XINTF zone 7 for 32 data transfer;  I modified the provided example function, so that XINTF uses 32 bit (respective GPIO's and XTIMING.bit.XSIZE=1)

    foo = 0xABCD2222;  //write 32 bit of data to zone 7

}

Problem:

When I look at the memory location of variable "foof", only the high 16 bit were transfered. The low 16 bit were overwritten, i.e. 0x0020FC00 (high 16bit) contains 0xABCD but 0x0020FC01 (low 16 bit) contains 0xFFEF. Moreover, performing this transfer seems to change the memory content of each odd adress in the whole zone!

Questions:

How do I have to perform 32 bit data transfer to or from a XINTF zone?

Do I have to manually manipulate adress pointers via assembler to perform this 32 bit access?

Could you please provide an example?

 

Thank you very much!

  • EDIT: Corrected typo - should be 32 data lines (not address lines)

    Martin said:
    I am using eZDSP with an 28355 DSC and tried to change the provided example "Example_2833xDMA_xintf_to_ram" from using 16 bit data transfer to using 32 bit data transfer. However, if I configure register XTIMING7.bit.XSIZE = 1,

    The XINTF XSIZE setting corresponds to how many data lines are used.  In 16 bit mode there are 16 data lines.  Working in this mode does not prevent you from doing a 32-bit read or write.  If you do a 32-bit transfer then the XINTF will automatically break it into  2 16-bit accesses.  

    When you switch to 32-bit mode then 32 data lines will be used.  The physical connection to the RAM has to be correct for this mode as shown in figure 5 of the XINTF ref guide.  On the eZdsp the external RAM is not connected in this manner so size 32 will not work. 

    -Lori

  • I think for 32-bit mode only XA1-XA18 (18 adress lines) and XWE1 (write enable line for high 16 Bit) are used (Fig 5 of XINTF reference guide)**. The data and adress lines are available on connector P2 and P10 of the eZdsp board. Therefore, I don't understand why 32-bit data exchange with an external peripheral should not be possible.

    I also tried to use zone 6 - as zone 7 should be connected to external SARAM on the eZdsp-board - but this did not work either.

    **I also switched SW2-1 off on eZdsp board to use GPIO28-GPIO31 for external interface (XA17-XA19).

  • Thank you for your answer! Now I got it - page A6 eZdsp manual. Of course I cannot perform 32-bit data transfer if coresponding data lines are not connected.

    Thanks!

  • Is it correct, that 32-bit mode should work for zone 6 or zone 0? Does the permanent connection of the adress XA0-XA16 and data lines XD0-XD15 to external SRAM on eZdsp disturb data transfer to any device, that is connected via P2 and P10? I still read wrong high 16-bit back in 32-bit mode for zone 0 as well as for zone 6.

     

    Martin

  • Martin said:

    Is it correct, that 32-bit mode should work for zone 6 or zone 0? Does the permanent connection of the adress XA0-XA16 and data lines XD0-XD15 to external SRAM on eZdsp disturb data transfer to any device, that is connected via P2 and P10? I still read wrong high 16-bit back in 32-bit mode for zone 0 as well as for zone 6.

     

    Martin

    Martin,

    On the eZdsp external SRAM is only connected to zone 7. 

    Each XINTF zone shares the same address and data lines, but has its own unique chip select signal (XZCS0n, XZCS6n, XZCS7n).  On the eZdsp, external SRAM is connected to zone 7 XZCS7n.  The other chip select signals go to the expansion header. 

    -Lori