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Help! execution time of C28x QMACL instruction with RPT

CHENGYUXIAN
Prodigy 140 points

In spru430d.pdf (TMS320C28x DSP CPU and Instruction Set Reference Guide), it take N+2 cycles the QMACL with RPT instruction. In fact, it take 10us execution times when QMACL repeat 512 times, when the C2808 CPU run at 100M, and all the loc32 and XAR7 all pointd to RAM with zero wait states. Is it true?

  • TI__Guru* 91145 points

    Make sure the operands pointed to by 'loc32' and XAR7 are in different SARAM blocks.  Each physical block of memory is single access so if you have both operands in the same memory block there will be pipeline stalls because both cannot be read at the same time.  If you have the operands in different memory blocks then each can be read at the same time.

    Lori

  • in reply to Lori Heustess
    Prodigy 140 points

    Lori:

    Thank you! The problem is solved with 'loc32' and XAR7 pointed to different SARAM blocks.

  • in reply to CHENGYUXIAN
    Mastermind 7585 points

    Just to add an additional comment to Lori:

    1)   According tho the QMACL instruction please also make sure that 'loc32' points to an operand in Data Memory and XA7 points to one in CODE memory. The 28x has 2 independent bus sysytems (code , data), and QMACL accesses both spaces simultaneously, providing you use the correct pointer setup.

    2) Please make sure that your operands are aligned to even addresses. The QMACL reads 32 bit each from code and data memory.

    Regards