Minimum interrupt latency of F280x, F2833x, Piccolo A

Wayne,

At 10 MHz interrupt, you have only 10 cycles between interrupts (at 100 MHz CPU).  Minimum interrupt response to actually be executing code in the ISR is ~14 cycles, and then you've got another ~10 cycles to return from the interrupt.  That adds up to 24 cycles.  So, you cannot do what you want.  Even if the total interrupt response was 0, you'd only have 10 cycle in the ISR to do any work.  That is really not enough to do anything useful.

Regards,

David

Wayne,

with a 10MHz PWM frequency, you only have 10cycles to do anything at 100MHz (6 cycles at 60MHz for Piccolo-A).

For the C28 CPU, it is about 12 cycles to respond to the interrupt (the time it takes to service the first instruction in the ISR). The CPU takes 8 cycles to do a context save and then 8 cycles to do a context restore. So that is 16 cycles that the CPU is savinga nd restoring. So in effect, there is no way you could service a 10MHz interrupt.

Why such a high PWM frequency?

What is the control loop bandwidth requirement?

There is a feature in the PWM peripherals where you can generate an interrupt every 2nd or 3rd period. This would give you 20 or 30 instructions between interrupts (or 12 to 18 instructions at 60MHz).

 On the up-coming PICCOLO-B, the CLA will have better interrupt response, it can respond to an interrupt in 6 cycles (@60MHz). If you generate an interrupt every 2nd or 3rd period, then the CLA has 12 or 18 instructions to respond and do something. Means the CPU is free to do other stuff.

Alternatively, there is the upcoming DELFINO device with 300MHz clock cycles. Then you have 30/60/80 instructions between interrupts based on interrupt period choice configurations.

Cheers,

Alex T.