tms320f28335 xintf consecutive write with buffering fails

Hello!

1 Could you please present your source code of XINTF configuration in greater detail?

2 Did you use manual 0068.TI_TMS320x2833_XINTFspru949d.pdf?

Regards,

Igor

Hi Igor,

1) I'll post detailed source in Monday. 

2) Yes, I read this manual many times quite carefully I think.. This is my first project with XINTF

Manual says that CPU will stall if write buffer is full and there is no need to worry about it in software.

I don't check WLEVEL or change WBUFF anywhere.

I think it's something to do with using READY input, maybe not..

For now I don't need write buffering but I've lost a lot of time to actually find what is the reason of strange behavior, so I'm wonder why..

Regards

Karol

 Hi,

 Code with 3 write buffering enabled which fails:

 
XINTF init function:

void XINTF_init(void)
{
// Configure GPIO64..87 as XINTF purpose (16-bit wide data bus)
EALLOW;
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0

GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7

GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18

GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW

GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6

// Make sure the XINTF clock is enabled
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;


// Timing for all zones
XintfRegs.XINTCNF2.bit.XTIMCLK = 1; // XTIMCLK = 1/2 SYSCLKOUT
XintfRegs.XINTCNF2.bit.WRBUFF = 3; // use 3 Write Buffer
//XintfRegs.XINTCNF2.bit.WRBUFF = 3; // Dont use Write Buffer
XintfRegs.XINTCNF2.bit.CLKOFF = 1; // XCLKOUT is disabled

// Zone 6 - external SRAM (AS7C34098A)
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 1;
XintfRegs.XTIMING6.bit.XWRACTIVE = 1;
XintfRegs.XTIMING6.bit.XWRTRAIL = 0;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 1;
XintfRegs.XTIMING6.bit.XRDACTIVE = 1;
XintfRegs.XTIMING6.bit.XRDTRAIL = 0;

// don't double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 0;

// Zone will not sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 0;
XintfRegs.XTIMING6.bit.READYMODE = 0;

XintfRegs.XTIMING6.bit.XSIZE = 3; // '3' - x16 data bus

// Zone 7
// When using ready in Async mode:
// Lead must always be 1 or greater, Active must be 2 or greater
// and Lead + Active >= 4 Tclk

// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 1;
XintfRegs.XTIMING7.bit.XWRACTIVE = 3;
XintfRegs.XTIMING7.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 1;
XintfRegs.XTIMING7.bit.XRDACTIVE = 3; //
XintfRegs.XTIMING7.bit.XRDTRAIL = 1;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;

XintfRegs.XTIMING7.bit.USEREADY = 1; // Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.READYMODE = 1; // XREADY input is asynchronous for the zone

XintfRegs.XTIMING7.bit.XSIZE = 3; // '3' - x16 data bus

EDIS;

//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");

 }

In linker command file
In section MEMORY: PAGE 1

ZONE6 : origin = 0x100000, length = 0x040000 /* XINTF zone 6 - 256k data space*/
ZONE7 : origin = 0x200000, length = 0x004000 /* XINTF zone 7 - 16k data space*/

Allocation of defined zones

/* Allocate 0x4000 of XINTF Zone 7*/
ZONE7DATA : > ZONE7, PAGE = 1
/* Allocate 0x40000 (256k) of XINTF Zone 6*/
ZONE6DATA : > ZONE6, PAGE = 1

In main source file

// ---- XINTF variables ----
#pragma DATA_SECTION(sramBuf,"ZONE6DATA");
volatile Uint16 sramBuf[0x40000]; // 256k x16 space in Zone6

#pragma DATA_SECTION(zone7buf,"ZONE7DATA");
volatile Uint16 zone7buf[0x4000]; // 16k x16 space in Zone7

Writing to Zone7 function:

void Zone7write(Uint16 offset, Uint16 *value)
{
zone7buf[offset+0] = value[0];
zone7buf[offset+2] = value[1];
zone7buf[offset+4] = value[2];
zone7buf[offset+6] = value[3];
zone7buf[offset+8] = value[4];
zone7buf[offset+10] = value[5];
zone7buf[offset+12] = value[6];
zone7buf[offset+14] = value[7];
zone7buf[offset+16] = value[8];
zone7buf[offset+18] = value[9];
zone7buf[offset+20] = value[10];
zone7buf[offset+22] = value[11];
zone7buf[offset+24] = value[12];
zone7buf[offset+26] = value[13];
zone7buf[offset+28] = value[14];
zone7buf[offset+30] = value[15];
}

As seen I'am also using Zone6 with external SRAM.

This zone works fine with write buffering enabled. I do consecutive write and read in for{} loop. 

I haven't checked asm file to see step by step instruction, probably there are some instruction between each write to Zone6.

Maybe why it's working with buffering

SRAM testing function:

Uint32 SRAM_test(void)
{
Uint32 i;
// Fill SRAM with data
for (i=0; i<0x40000; i++)
{
sramBuf[i] = (Uint16)(i+1);
}
// Check SRAM content
for (i=0; i<0x40000; i++)
{
if (sramBuf[i] != (Uint16)(i+1))
{
return i; // return address where fail
}
}

Regards

Karol

Hello Karol!

Maybe it does not effect, but you configure Zone 7 at Asynchronous Mode (USEREADY = 1, READYMODE = 1). For this mode valide values are  XRDTRAIL = 0, XWRTRAIL =0 (you use 1 for bouth). It is all at now...

Regards,

Igor

Igor, thanks for advice.

Yes, according to documentation, Trail settings for (USEREADY = 1, READYMODE = 1) should be set to 0.

I've tried this (set XRDTRAIL = 0, XWRTRAIL =0) but unfortunately it doesn't help..

It works the same, with write buffering enabled (set to 3) write fails (some incorrect values).

Regards

Karol 

Hi Karol!

I don't know the features of your project, but you have written that Zone 6 works correctly. Perhaps my question is strange. What reason is in different configurations for Zone 6 & 7? Maybe Zone 7 needs to configure like Zone 6 or I'm wrong?

Regards,

Igor

 Hi Igor,

No, I can't configure Zone 7 as Zone6. Peripheral on Zone 7 have it's BUSY line (connected to READY on XINTF) and I have to manage it.

BUSY timing is variable and I can't event predict maximum BUSY time unfortunately.

I don't actually need write buffering, without everything works fine.

Thanks for help 

Regards