F2812 XINTF Write Buffer Timing Details

Subramanyam Kasibhat said:

We have a board with TMS320F2812 DSP interfacing an ARINC Chip (HOLT 3582) on the XINTF.

Observation:

1. When the write buffer level is set to 1, the first write on XINTF is not visible on the Logic Analyzer. Writes post the first word are visible as described in the XINTF Interface document.

2. When the write buffer level is set to 2, the first two writes on XINTF are not visible on the Logic Analzer!

Is there any document available with timing details of XINTF wiht write buffer level enabled? In out configuration we have the XREADY pin controlled by the external device or can be controlled by the 2812 itself. We have connected a GPIO from 2812 to the XREADY Pin. We plan to use a timer interrupt to change the XREADY Pin Status if we opt to use the DSP to control it. We hope to have the Data Lines active during this phase.

Regards,

Subbu

Subbu,

The timing of XINTF with the write buffer is the same as when no buffering is enabled.  That is, it follows the normal lead-active-trail timing.  The only difference is the CPU pipeline itself is not stalled while the write is going out the XINTF.

Some things to try:

Do *any* of the strobes go low when you do the write? (i.e. chip select, write strobe)

If you don't control the XREADY line (ie just tie it high) do you see the writes as you expect?

Regards,

-Lori 

Lori,

Thanks for your quick help.  I guess its an understanding issue form my side. Looks like the XINTF is working as it should.

Regards,

Subbu

Hello !

I have an old design using the 28f12 dsp . I have received a similar project as before doyou recommend to use the 2812 or replace it with a different dsp. If yes which dsp would you recommend?

Regards Arye