TMS320F28335: WRITE A 32bit with XINTF 16bit data bus - F28335

Hi, 

I have a problem with writing a 32-bit "long int" variable.

I have configured and verified the XINTF 16bit data bus, in fact, the 16-bit "int" writes are executed correctly.

But when i define a long end i try to write it into a external memory, this happens to me: 
the 16 bits of the lower part are written to the top of the external memory and the lower part of the external memory is populated by FFFF.

So when I try to write a long value 0x12345678 into external memory i read => 0x5678FFFF.

If instead of creating a long, i create two int variables and i manage it as two write a 16bit, i have no problems, but I would be very useful to treat them as a long one.

I supposet that a 32-bit transfer then the XINTF will automatically break it into 2 16-bit accesses, is correct?  

Any suggestion?

Thanks

Marco

My configuration is:

void init_zone7(void)
{

// Configure the GPIO for XINTF with a 16-bit data bus
// This function is in DSP2833x_Xintf.c
InitXintf16Gpio();

EALLOW;
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT/2
//Source clock is 1/2 systemclock, so 75MHz (13,33ns CLK cycle)
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// No Write buffer
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 1;
// XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKMODE = 0;
// Disable XHOLD to prevent XINTF bus from going into high impedance state
// whenever TZ3 signal goes low. This occurs because TZ3 on GPIO14 is
// shared with HOLD of XINTF
XintfRegs.XINTCNF2.bit.HOLD = 1;

// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 2;
XintfRegs.XTIMING7.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 3;
XintfRegs.XTIMING7.bit.XRDTRAIL = 1;

// don't double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;

// Zone will not sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 0;
XintfRegs.XTIMING7.bit.READYMODE = 0;

// 1,1 = x16 data bus
// 0,1 = x32 data bus
// other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
EDIS;

// Bank switching
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;

//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
__asm(" RPT #7 || NOP");

}