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I am trying to set GPIO12 as a TZ1 pin on a 64 pin 28035 and have it set the OSHT1 flag on a ePwm4 module, but even though the pin is going low the OSHT1 is never set.
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; //set IO to TZ1
make sure you configure these registers inside of
EALLOW;
// make secure register changes after EALLOW
EDIS;
the set-up of your ePWM Trip Zone is correct
EPwm4Regs.TZSEL.bit.OSHT1 = 1; //enable TZ1 for OSHT
for the action on the event we usualy do it like this
EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
Hi,
Have you taken a look at the below example? I would recommend experimenting with it.
\controlSUITE\device_support\f2806x\v141\F2806x_examples_ccsv5\epwm_trip_zone\
I also have a few thoughts which may help you find your issue:
* There isn't specifically a OSHT2 flag. You'll have to look at TZFLG[OSHT] (which is the flag showing that a OSHT has occurred).
* Is the PWM clock enabled?
Thank you,
Brett
The problem is that everything is working properly F28027. I have the feeling that this module F28069 all off. I used the other pins to check trip zone: in the debugger can be seen that at pin logic 0, but TZFLG[OSHT] flag is not set. Maybe something I have not included. Let us once again:
PieVectTable.EPWM1_TZINT = &epwm1_tzint_isr; IER |= M_INT2; // Enable CPU Interupt 2 PieCtrlRegs.PIEIER2.bit.INTx1 = 1; // Enable INT 2.1 (EPWM1_TZINT) in the PIE GpioCtrlRegs.GPAPUD.bit.GPIO16=1; // disable pull-up on GPIO16(FO_OUT) GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ2) GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ2 EPwm1Regs.TZSEL.bit.OSHT2 = 1; //TZ2 EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;// What do when TZ2 occurs EPwm1Regs.TZEINT.bit.CBC = 1; // Enable TZ interrupt EPwm_Config(); //enable PWM module, some configs etc
In debug mode I checked the contents of the registers: write to them passes. Why processor see logic 0, but does not set the flag. Most likely I'm missing some bits.