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TMS320F28035: TZ1 EPWM1_TZINT interrupt flag not being set.

Soham Karyakarte19
Prodigy 100 points
Part Number: TMS320F28035

I am trying to stop a PWM on the occurrence of an external stop signal by tripzone and need to execute a few more things in the trip interrupt service routine. 

I have configured tz1 as a OST interrupt for tz1' at GPIO15. 

On the occurrence of 0 at GPIO15 the ePWM1 is tripped. However the TZ_INT isr is not executed. 

The reason for this is that pie vector table group 2 flag is not raised and also the IFR INT2 flag is not raised. 

In my code I have the following related commands. 

PieVectTable.EPWM1_TZINT = &tzint;

PieCtrlRegs.PIEIER2.bit.INTx1 = 1;

PieCtrlRegs.PIEACK.all = 0xFFFF;

PieCtrlRegs.PIECTRL.bit.ENPIE = 1;

IER |= M_INT2;

EPwm1Regs.TZEINT.bit.OST = 1;

They have many lines of code inbetween and wherever required EALLOW; and EDIS; is performed. 

On implementation, when I externally try to trip the ePWM, it is tripped however the service routine is not executed. 

The following are flag register contents:

IER = 0x0207
IFR = 0x0004

ePWM1.TZSEL = 0x0100
ePWM1.TZCTL = 0x000A
ePWM1.TZFLG = 0x0005
ePWM1.TZEINT = 0x0004

PIEACK = 0x0006
PIEIER2 = 0x0001
PIEIFR2 = 0x0000

So the IFR and PIEIFR2 themselves do not reflect the occurrence of an interrupt. Whereas ePWM1.TZFLG does reflect that interrupt is encountered. 

As a result the interrupt service routine is not run. 

Thanks in advance.

  • 0
    TI__Mastermind 42195 points

    Soham,

    could you read back your configuration using the memory browser? If PIEIFR is not set and the TZFLG is set I think TZEINT may not be set.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Prodigy 100 points
    Thank you Cody,

    I figured out that both PIEIFR and IFR have their respective flags set and the content in the tzint() interrupt routine is executed and both these flags are turned off after the execution.
  • 0 in reply to Soham Karyakarte19
    Prodigy 100 points

    Cody,

    However the problem is something else.

    interrupt void tzint(void)
{


	EPwm3Regs.CMPA.half.CMPA = PERIOD_MAX*4 + 1;
	EPwm3Regs.CMPB = PERIOD_MAX*4 + 1;

	EPwm3Regs.TBCTL.bit.CLKDIV = 7;
	EPwm3Regs.TBCTL.bit.HSPCLKDIV = 7;


	// Enable CNT_zero interrupt using EPWM1 Time-base
    EPwm3Regs.ETSEL.bit.INTEN = 1;   // Enable EPWM1INT generation
    EPwm3Regs.ETSEL.bit.INTSEL = 1;  // Enable interrupt CNT_zero event
    EPwm3Regs.ETPS.bit.INTPRD = 1;   // Generate interrupt on the 1st event
	EPwm3Regs.ETCLR.bit.INT = 1;     // Enable more interrupts


	GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;


	PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

}

interrupt void tzisr(void)
{
	InitPwm3();

	EPwm3Regs.CMPA.half.CMPA = PERIOD_MAX*1;
	EPwm3Regs.CMPB = PERIOD_MAX*1;

	GpioDataRegs.GPASET.bit.GPIO8 = 1;

	// Clear EPwm1 INT flag
    EPwm3Regs.ETCLR.bit.INT = 1;

	EPwm1Regs.TZCLR.bit.OST = 1;

	EPwm1Regs.TZCLR.bit.INT = 1;

	AckPwmInterrupt();		//acknowledge PWM interrupt

}

    In the above code, tzint is the trip zone interrupt routine and  tzisr is the epwm3 interrupt routine. tzint enables epwm3 interrrupt. tzisr aims on clearing all tz flags and resuming epwm1.

    The respective flags PIEFR2 and IFR are set and reset when the routine is executed. But the TZFLG[OST] still stays 'on' even after putting TZCLR[OST]=1 and TZCLR[INT]=1. 

    As a result, the ePWM1 stops altogether even after execution of tzisr. 

    Thank you 

  • 0 in reply to Soham Karyakarte19
    TI__Mastermind 42195 points

    Soham,

    When you say:

    Soham Karyakarte19 said:
    But the TZFLG[OST] still stays 'on' even after putting TZCLR[OST]=1 and TZCLR[INT]=1. 

    Are you referring to ePWM3's OST flag? It looks like you are clearing ePWM1's flag.

     // Clear EPwm1 INT flag 

EPwm3Regs.ETCLR.bit.INT = 1; 
EPwm1Regs.TZCLR.bit.OST = 1; 
EPwm1Regs.TZCLR.bit.INT = 1;

    Regards,
    Cody

  • 0 in reply to Cody Watkins
    Prodigy 100 points
    Hello Cody,

    That's exactly what I am saying. My commands do indicate that TZCLR[OST] and TZCLR[INT] for 'ePWM1' are getting cleared.

    But the debug interface on CCS does not reflect that. TZFLG[OST]=1 and TZFLG[INT]=1 even after execution of the 'tzisr' routine.

    Naturally, it does not trigger the 'tzint' again as the flags are already 'on'.

    Thank you in advance.
  • 0 in reply to Soham Karyakarte19
    TI__Mastermind 42195 points

    Soham,

    what is the status of your EALLOW bit when you are executing the instructions?

    You should have an EALLOW before and an EDIS after.

    Regards,
    Cody