Hi,
I am trying to utilize both ADC1 and ADC2 in the F28M36 Core. The setup is based on the Concerto Control Card and I am running into an issue that I couldn't solve.
The issue is very simple, configure all available channels for ADC1 and ADC2 and sample them using a trigger such as PWM1 compare event. When ADC1 is configured for this every thing works fine but if the same code is used to utilize the ADC2 module, no interrupts are generated. Please see the code below and provide insight into why the different behavior and why ADC2 is not able to generate EOC interrupts.
The following piece of code works fine and triggers the conversion interrupts as expected.
void ConfigAdc(void)
{
InitAdc1();
InitAdc2();
Adc1OffsetSelfCal();
Adc2OffsetSelfCal();
LoopCount = 0;
ConversionCount = 0;
g_c28EventCounter.cAdc1 = 0;
g_c28EventCounter.cAdc2 = 0;
// Configure ADC
EALLOW;
Adc1Regs.ADCSAMPLEMODE.all = 0x3F;
// Enable simultaneous sampling.
Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1;
// Enable non-overlap mode i.e. conversion and future sampling events dont overlap
Adc1Regs.ADCCTL1.bit.INTPULSEPOS = 1;
// ADCINT1 trips after AdcResults latch
Adc1Regs.INTSEL1N2.bit.INT1E = 1;
// Enabled ADCINT1
Adc1Regs.INTSEL1N2.bit.INT1CONT = 0;
// Disable ADCINT1 Continuous mode
Adc1Regs.INTSEL1N2.bit.INT1SEL = 0;
// setup EOC0 to trigger ADCINT1 to fire
AnalogSysctrlRegs.TRIG1SEL.all = 5;
// Assigning EPWM1SOCA to ADC TRIGGER 1 of the ADC module
Adc1Regs.ADCSOC0CTL.bit.CHSEL = 0;
// set SOC0 channel select to ADC2A0/ADC2B0
Adc1Regs.ADCSOC0CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc1Regs.ADCSOC0CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc1Regs.ADCSOC1CTL.bit.CHSEL = 2;
// set SOC1 channel select to ADC2A2/ADC2B2
Adc1Regs.ADCSOC1CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc1Regs.ADCSOC1CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc1Regs.ADCSOC2CTL.bit.CHSEL = 3;
// set SOC0 channel select to ADC2A3/ADC2B3
Adc1Regs.ADCSOC2CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc1Regs.ADCSOC2CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc1Regs.ADCSOC3CTL.bit.CHSEL = 4;
// set SOC1 channel select to ADC2A4/ADC2B4
Adc1Regs.ADCSOC3CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc1Regs.ADCSOC3CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc1Regs.ADCSOC4CTL.bit.CHSEL = 6;
// set SOC0 channel select to ADC2A7/ADC2B7
Adc1Regs.ADCSOC4CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc1Regs.ADCSOC4CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc1Regs.ADCSOC5CTL.bit.CHSEL = 7;
// set SOC1 channel select to ADC2A7/ADC2B7
Adc1Regs.ADCSOC5CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc1Regs.ADCSOC5CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
EDIS;
}
Where as the code shown below utilizes ADC2 module but everything else remains the same and it does not work.
void ConfigAdc(void)
{
InitAdc1();
InitAdc2();
Adc1OffsetSelfCal();
Adc2OffsetSelfCal();
LoopCount = 0;
ConversionCount = 0;
g_c28EventCounter.cAdc1 = 0;
g_c28EventCounter.cAdc2 = 0;
// Configure ADC
EALLOW;
Adc2Regs.ADCSAMPLEMODE.all = 0x3F;
// Enable simultaneous sampling.
Adc2Regs.ADCCTL2.bit.ADCNONOVERLAP = 1;
// Enable non-overlap mode i.e. conversion and future sampling events dont overlap
Adc2Regs.ADCCTL1.bit.INTPULSEPOS = 1;
// ADCINT1 trips after AdcResults latch
Adc2Regs.INTSEL1N2.bit.INT1E = 1;
// Enabled ADCINT1
Adc2Regs.INTSEL1N2.bit.INT1CONT = 0;
// Disable ADCINT1 Continuous mode
Adc2Regs.INTSEL1N2.bit.INT1SEL = 0;
// setup EOC0 to trigger ADCINT1 to fire
AnalogSysctrlRegs.TRIG1SEL.all = 5;
// Assigning EPWM1SOCA to ADC TRIGGER 1 of the ADC module
Adc2Regs.ADCSOC0CTL.bit.CHSEL = 0;
// set SOC0 channel select to ADC2A0/ADC2B0
Adc2Regs.ADCSOC0CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc2Regs.ADCSOC0CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc2Regs.ADCSOC1CTL.bit.CHSEL = 2;
// set SOC1 channel select to ADC2A2/ADC2B2
Adc2Regs.ADCSOC1CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc2Regs.ADCSOC1CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc2Regs.ADCSOC2CTL.bit.CHSEL = 3;
// set SOC0 channel select to ADC2A3/ADC2B3
Adc2Regs.ADCSOC2CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc2Regs.ADCSOC2CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc2Regs.ADCSOC3CTL.bit.CHSEL = 4;
// set SOC1 channel select to ADC2A4/ADC2B4
Adc2Regs.ADCSOC3CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc2Regs.ADCSOC3CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc2Regs.ADCSOC4CTL.bit.CHSEL = 6;
// set SOC0 channel select to ADC2A7/ADC2B7
Adc2Regs.ADCSOC4CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc2Regs.ADCSOC4CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
Adc2Regs.ADCSOC5CTL.bit.CHSEL = 7;
// set SOC1 channel select to ADC2A7/ADC2B7
Adc2Regs.ADCSOC5CTL.bit.TRIGSEL = 5;
// Set Trigger 1 for Start of Conversion.
Adc2Regs.ADCSOC5CTL.bit.ACQPS = 6;
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
EDIS;
}