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Piccolo 28022 Errata

Natallia Holubeva1
Expert 6550 points

Hello e2e,

I have a question about one of the errata for the Piccolo 28022.  It’s the ADC:  Initial Conversion advisory on page 8 of the errata sheet.  There are some details about  Rev A silicon at CPU clocks of 40MHz and 60MHz, but nothing about 50MHz, which is what we are using.  Does this mean that the Rev A silicon at 50MHz does NOT have this problem?

We aren’t doing anything special to work around this errata and things seem to work fine. But I’m looking for confirmation to be sure this doesn’t show up at some point in the future.

Thank you

  • 0
    TI__Guru 60865 points

    Hi Natallia,

    The initial conversion issue exists for any ADCCLK > 30MHz.  The magnitude is VTP (and ADCCLK frequency) dependent and it can go from not occurring at all to occurring every sample based on small timing changes in the software, so I recommend that you definitely use the workarounds.

    The two possible workarounds are:

    *Discard the first sample of each set of conversions.  This is usually the best bet when a group of conversions needs to sample more than 2 channels.

    *Set the ADC in /2 clock mode (ADCCLK <= 30MHz) and in non-overlap mode.  This is usually the best bet when triggers to the ADC cause only 1 or 2 conversions at a time for each trigger.

  • 0 in reply to Devin Cottier
    Prodigy 240 points

    Hi,

    I'm the engineer who originally posed this question to my FAE - I'm sure it's my original question because it's verbatim from the email I sent my FAE.  I'd like to pose a follow-up question.

    We are currently performing 6 A/D conversions.  Two are single conversions using SOC0 and SOC1, and 2 are simultaneous conversions using SOC2/3 and SOC4/5.  We are receiving a new board spin soon that will require 2 additional single conversions using SOC6 and SOC7. All conversions are triggered from EPWM2 SOCA.  I’d like to keep the A/D conversion time as short as possible since we are adding more conversions.  Therefore I’d rather not set the ADC in /2 clock mode unless absolutely necessary.

    Could I work around this by setting up SOC0 as a dummy conversion (have it convert a channel that we aren't using), move the channel I'm currently converting via SOC0 to SOC8, and leave my SOC1, SOC2/3. SOC4/5, SOC6, and SOC7 conversions as-is?  I would leave the ADCNONOVERLAP = 0 and CLKDIV2EN =0 to allow 50MHz ADC clock and to allow overlap of sample and conversion.  I would never bother to read the ADCRESULT0 generated by the dummy SOC0 read.  If all SOCs are triggered by EPWM2 SOCA,  the dummy SOC0 would always occur first.  Would this work?

    Thanks!

  • 0 in reply to Matt Ellis1
    TI__Guru 62975 points

    Matt,

    The scenario that you described should work.  As long as the conversions are initiated by the same trigger, you just need to ignore the first single SOC (or first simultaneous pair of SOCs).

    -Tommy

  • 0 in reply to tlee
    Prodigy 240 points

    OK, thanks very much!

    Matt