Use C2000 Delfino F2837xD as SPI Slave to read Bitstream

user4146006

Other Parts Discussed in Thread: CONTROLSUITE

Hi,

I'm trying to read in a bitstream via the SPI module and hand it over via DMA. A fist step is to only read it in the FIFO and check the function of the SPI.

The Bitstream has a 10MHz clock signal

I decided to go for:

-Slave Network Mode

-FIFO buffers to read in (8bit or 16bit)

-SPI A

-High-Speed Mode

I cannot get any data inside, when debugging I cannot see any changes in the FIFO Status bits or SPI RX Data

I tried it with Pull ups on and off, no difference

The clk is connected to GPIO 60 SPICLK

The Bitstream to GPIO 58 SPISIMOA

SPISTEA is on GPIO61 a wire to GND or 3.3V didnot change anything

Here is my GPIO settings as it is recommended in the technical reference Table 7-7

   EALLOW;

    GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0x11; // Configure GPIO58 as SPISIMOA
    GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 0x11; // Configure GPIO59 as SPISOMIA
    GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 0x11; // Configure GPIO60 as SPICLKA
    GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0x11; // Configure GPIO61 as SPISTEA

    GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 0x11; // Configure GPIO58 as SPISIMOA High-Speed Mode
    GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 0x11; // Configure GPIO59 as SPISOMIA High-Speed Mode
    GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 0x11; // Configure GPIO60 as SPICLKA High-Speed Mode
    GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 0x11; // Configure GPIO61 as SPISTEA High-Speed Mode

    EDIS;

and here my settings for the SPI registers:

   ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 0;

   SpiaRegs.SPICCR.bit.SPISWRESET = 0;       // set SPI to Reset

   // FIFO configuration

   SpiaRegs.SPIFFCT.all = 0;               // place SPI FIFO in reset , clear SPIFFCT (control register FIFO)
   for(m=0;m<3;m++); // wait ??
   SpiaRegs.SPIFFTX.bit.SPIFFENA = 0x1;   // FIFO mode enable
   SpiaRegs.SPIFFRX.all = 0;     // clear FFRX register
    SpiaRegs.SPIFFRX.bit.RXFFIL = 0x8;       // Set RX FIFO level
   SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1;   // FIFO RX release


   // SPI configuration

   // already done by default
   SpiaRegs.SPICTL.bit.MASTER_SLAVE = 0;    // Network Mode = Slave
   SpiaRegs.SPICTL.bit.TALK = 0;           // only receive, SPISOMI is put into the high-impedance state

   // other then default
   SpiaRegs.SPICCR.all = 0;               // Clear SPI control register, SPI in reset
   SpiaRegs.SPICCR.bit.SPICHAR = 0x7;        // 0xF 16bit words, 0x7 8bit words
   SpiaRegs.SPICCR.bit.CLKPOLARITY = 0x1;
   //SpiaRegs.SPICCR.bit.HS_MODE = 0x1;        // enable High-Speed Mode for SPI, set bit 5

   SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 17;                   //
   //SpiaRegs.SPICCR.all = 0x009F ;               // Release SPI from Reset, enable LB mode
   SpiaRegs.SPICCR.bit.SPISWRESET = 0x1;   // Release SPI from Reset

The input signal looks good on scope and I do not really know where to look at next.

Does anybody see my mistake or do you have an idea for debugging?

Thank you

Georg

Thanks Georg

over 10 years ago

0 Mark Labbato over 10 years ago

Guru 30330 points

George,

I have a few things.
You must configure the GPyGMUX1/2 registers before the GPyMUX1/2. This is to avoid a glitch on any other mux option.
Please configure the GPyQSEL1/2 registers appropriately for your inputs. The input qualification may impact the SPI receiving data properly.

Have you been able to run the SPI examples in controlSuite?

-Mark

0 user4146006 over 10 years ago in reply to Mark Labbato

Prodigy 60 points

Hi Mark,

thanks for your remarks. Did the changes as you suggested.

I tested SPI example loopback dma.

Today I built a dma and loopback mode in my project and it worked fine.
But when I do the following changes I get back to my original problem discription, no changes in status registers at all.
(I tried to change as little as possible relative to the working loop back with dma example.)

in SPICTL
change to Slave mode
disable TALK bit

in SPICCR
disable Loopback mode

The dma does not create an interrupt anymore. Seems like nothing is getting in. Doublechecked the Signals on the scope again, everything looks good.

How can I check the input of the signal in the uC, any idea?

Thank you
Georg

0 Manoj Santha Mohan over 10 years ago in reply to user4146006

TI__Guru 55700 points

spi_function.c

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#include "F2837xD_device.h"     // F2837xD Headerfile Include File
void SpiaSlaveConfig(void)
{
    EALLOW;
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;     //SPI software reset
    SpiaRegs.SPICCR.bit.SPICHAR = 0;        //SPI character length 1 bit
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 0;   //SPI (SLAVE)
    SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0;  //SPI receive overrun interrupt
    //SpiaRegs.SPICTL.bit.SPIINTENA = 1;      //SPI data ready interrupt enable
    SpiaSlaveFifoConfig();
    SpiaRegs.SPICCR.bit.SPISWRESET = 1;     //Release SPI software reset
    EDIS;
}
void SpiaSlaveFifoConfig(void)
{
    EALLOW;
    SpiaRegs.SPIFFTX.bit.SPIFFENA    = 1;   //Enable SPI FIFO
    SpiaRegs.SPIFFTX.bit.SPIRST      = 1;   //SPI FIFO can TX (or) RX
    SpiaRegs.SPIFFRX.bit.RXFIFORESET = 0;   //Reset FIFO pointer to 0
    SpiaRegs.SPIFFRX.bit.RXFFIENA    = 1;   //Enable RX FIFO interrupt
    SpiaRegs.SPIFFRX.bit.RXFFIL      = 0x10;//Generate RX FIFO interrupt after receving 16 words
    SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1;   //Enable RX FIFO operation
    EDIS;
}
/*
void SpibMasterConfig(void)
{
    EALLOW;
    SpibRegs.SPICCR.bit.SPISWRESET = 0;     //SPI software reset
    SpibRegs.SPICCR.bit.SPICHAR = 0xF;      //SPI character length 16 bit
    SpibRegs.SPICTL.bit.MASTER_SLAVE = 1;   //SPI (Master)
    SpibMasterFifoConfig();
    SpibRegs.SPICCR.bit.SPISWRESET = 1;     //Release SPI software reset
    EDIS;
}
void SpibMasterFifoConfig(void)
{
    EALLOW;
    SpibRegs.SPIFFTX.bit.SPIFFENA    = 1;   //Enable SPI FIFO
    SpibRegs.SPIFFTX.bit.SPIRST      = 1;   //SPI FIFO can TX (or) RX
    SpibRegs.SPIFFTX.bit.TXFIFO      = 1;   //Release TX FIFO from reset
    SpibRegs.SPIFFTX.bit.TXFFIENA    = 1;   //Enable TX FIFO interrupt
    SpibRegs.SPIFFRX.bit.RXFIFORESET = 0;   //Reset FIFO pointer to 0
    SpibRegs.SPIFFRX.bit.RXFFIENA    = 1;   //Enable RX FIFO interrupt
    SpibRegs.SPIFFRX.bit.RXFFIL      = 0x10;//Generate RX FIFO interrupt after receving 16 words
    SpibRegs.SPIFFRX.bit.RXFIFORESET = 1;   //Enable RX FIFO operation
    EDIS;
}
*/
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#include "F2837xD_device.h"     // F2837xD Headerfile Include File

void SpiaSlaveConfig(void)
{
	EALLOW;
	SpiaRegs.SPICCR.bit.SPISWRESET = 0;		//SPI software reset
	SpiaRegs.SPICCR.bit.SPICHAR = 0; 		//SPI character length 1 bit

	SpiaRegs.SPICTL.bit.MASTER_SLAVE = 0; 	//SPI (SLAVE)
	SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0; 	//SPI receive overrun interrupt
	//SpiaRegs.SPICTL.bit.SPIINTENA = 1;      //SPI data ready interrupt enable

	SpiaSlaveFifoConfig();
	SpiaRegs.SPICCR.bit.SPISWRESET = 1;		//Release SPI software reset
	EDIS;
}

void SpiaSlaveFifoConfig(void)
{
	EALLOW;
	SpiaRegs.SPIFFTX.bit.SPIFFENA    = 1;	//Enable SPI FIFO
	SpiaRegs.SPIFFTX.bit.SPIRST   	 = 1;	//SPI FIFO can TX (or) RX

	SpiaRegs.SPIFFRX.bit.RXFIFORESET = 0;	//Reset FIFO pointer to 0
	SpiaRegs.SPIFFRX.bit.RXFFIENA	 = 1;	//Enable RX FIFO interrupt
	SpiaRegs.SPIFFRX.bit.RXFFIL		 = 0x10;//Generate RX FIFO interrupt after receving 16 words

	SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1;	//Enable RX FIFO operation
	EDIS;
}

/*

void SpibMasterConfig(void)
{
	EALLOW;
	SpibRegs.SPICCR.bit.SPISWRESET = 0;		//SPI software reset
	SpibRegs.SPICCR.bit.SPICHAR = 0xF; 		//SPI character length 16 bit

	SpibRegs.SPICTL.bit.MASTER_SLAVE = 1; 	//SPI (Master)

	SpibMasterFifoConfig();
	SpibRegs.SPICCR.bit.SPISWRESET = 1;		//Release SPI software reset
	EDIS;
}

void SpibMasterFifoConfig(void)
{
	EALLOW;
	SpibRegs.SPIFFTX.bit.SPIFFENA    = 1;	//Enable SPI FIFO
	SpibRegs.SPIFFTX.bit.SPIRST   	 = 1;	//SPI FIFO can TX (or) RX

	SpibRegs.SPIFFTX.bit.TXFIFO      = 1;	//Release TX FIFO from reset
	SpibRegs.SPIFFTX.bit.TXFFIENA    = 1; 	//Enable TX FIFO interrupt


	SpibRegs.SPIFFRX.bit.RXFIFORESET = 0;	//Reset FIFO pointer to 0
	SpibRegs.SPIFFRX.bit.RXFFIENA	 = 1;	//Enable RX FIFO interrupt
	SpibRegs.SPIFFRX.bit.RXFFIL		 = 0x10;//Generate RX FIFO interrupt after receving 16 words

	SpibRegs.SPIFFRX.bit.RXFIFORESET = 1;	//Enable RX FIFO operation
	EDIS;
}
*/

spi_sdfm_example.c

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#include "F28x_Project.h"
void SpiConfig(void);
void SpiFifoConfig(void);
interrupt void SPIATransmitISR(void);
interrupt void SPIAReceiveISR(void);
#define SPIFIFOLENGTH 16
#define MAX_LENGTH 0x1000
Uint16 i,rdata[SPIFIFOLENGTH];
Uint16 SD_DATA[MAX_LENGTH];
#pragma DATA_SECTION(SD_DATA,"SDdataFile");
#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile");
int main(void) {
    
    InitSysCtrl();
    InitSpiaGpio();
    GPIO_SetupPinOptions(19,GPIO_OUTPUT,GPIO_ASYNC);
    EALLOW;
    GpioDataRegs.GPACLEAR.bit.GPIO19 = 1;
    EDIS;
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();
    EALLOW;
    PieVectTable.SPIA_TX_INT = &SPIATransmitISR;
    PieVectTable.SPIA_RX_INT = &SPIAReceiveISR;
    EDIS;
    PieCtrlRegs.PIEIER6.bit.INTx1 = 1;
    PieCtrlRegs.PIEIER6.bit.INTx2 = 1;
    IER |= 0x0020;
    EINT;
    for(i=0;i<SPIFIFOLENGTH;i++)
    {
        rdata[i] = 0x7625;
    }
    SpiaSlaveConfig();
    for(;;);
}
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#include "F28x_Project.h"

void SpiConfig(void);
void SpiFifoConfig(void);

interrupt void SPIATransmitISR(void);
interrupt void SPIAReceiveISR(void);

#define SPIFIFOLENGTH 16
#define MAX_LENGTH 0x1000

Uint16 i,rdata[SPIFIFOLENGTH];

Uint16 SD_DATA[MAX_LENGTH];

#pragma DATA_SECTION(SD_DATA,"SDdataFile");

#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile");


int main(void) {
	
	InitSysCtrl();

	InitSpiaGpio();

	GPIO_SetupPinOptions(19,GPIO_OUTPUT,GPIO_ASYNC);

	EALLOW;
	GpioDataRegs.GPACLEAR.bit.GPIO19 = 1;
	EDIS;

	DINT;

	InitPieCtrl();

	IER = 0x0000;
	IFR = 0x0000;

	InitPieVectTable();

	EALLOW;
	PieVectTable.SPIA_TX_INT = &SPIATransmitISR;
	PieVectTable.SPIA_RX_INT = &SPIAReceiveISR;
	EDIS;

	PieCtrlRegs.PIEIER6.bit.INTx1 = 1;
	PieCtrlRegs.PIEIER6.bit.INTx2 = 1;

	IER |= 0x0020;

	EINT;

	for(i=0;i<SPIFIFOLENGTH;i++)
	{
		rdata[i] = 0x7625;
	}


	SpiaSlaveConfig();

	for(;;);

}





interrupt void SPIATransmitISR(void)
{
	ESTOP0;
}

interrupt void SPIAReceiveISR(void)
{
	static counter=0;

	EALLOW;
	for(i=0;i<=SPIFIFOLENGTH-1;i++)
	{
	   SD_DATA[counter+i]= (SpiaRegs.SPIRXBUF&1);     // Read data

	}

	counter = counter + SPIFIFOLENGTH;

	if(counter>=0x1000)
	{
		ESTOP0;
	}

    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1;  // Clear Overflow flag
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1;  // Clear Interrupt flag
	PieCtrlRegs.PIEACK.all|=0x20;       // Issue PIE ack
	EDIS;
}

Georg,

I believe you are trying to read SD bit stream using SPI. If so, you can use the attached code as reference. In the example code attached, I'm using using CPU to SPI data after my FIFO is full.

Regards,

Manoj

0 Matthew Overlin over 8 years ago in reply to Manoj Santha Mohan

Prodigy 50 points

Can someone point me to the best example from Control Suite where the F2837xD is a SPI slave. Or, if this person's example that now works, can you kindly provide the files from your project so I can try to re-create it for my purposes?

Thanks!

Matt

0 Mark Labbato over 8 years ago in reply to Matthew Overlin

Guru 30330 points

Matt,

At the moment, we do not have a SPI example in slave mode, this has already been added to our backlog, but I have no expected completion date.

The spi_function.c file that Manoj linked above does have the SPI configured for slave. You can plug those functions in to a fresh example and get started from there. The corresponding master functions are included as well, so you have the configuration for both ends of the communication.

If you have further questions, please create a new post on the matter and link back to this thread.

0 user4146006 over 8 years ago in reply to Matthew Overlin

Prodigy 60 points

Hallo Matt,

Back then I ended up with a different setup. So I did not need the SPI in Slave mode anymore.
I also did not safe my test code for this option and cannot even remember if it worked.

Sorry, cannot help with this one

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Use C2000 Delfino F2837xD as SPI Slave to read Bitstream