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I am working on SPI Master with 28335 controller and SPI slave with same controller.

J rajesh
Prodigy 150 points

I am working on SPI Master with 28335 controller  and SPI slave with same controller.  Master is in polling and Slave is in interrupt mode.
Following is the code for Master.

bool spidrvA_ReceiveCmdResponse_vd(uint16_t responseLen_u16)
{
   uint16_t index_u16 =0;
   uint16_t recvLength_u16 = 0;
   uint16_t dummyData_u16 = SPI_DUMMY_WORD;

   recvLength_u16 = responseLen_u16;
   for(index_u16=0;index_u16<recvLength_u16-1;index_u16++)
   {
     SpiaRegs.SPITXBUF = dummyData_u16;
     while(SpiaRegs.SPISTS.bit.INT_FLAG != 1);             // 9.2 us
     rxdata_u16a[index_u16] = SpiaRegs.SPIRXBUF;
     delay_vd(1);           //11.2 us
   }
   return 1;
}

In the above function there is function call delay_vd(1), If this function is commented, then Master is not able to receive the data.
while(SpiaRegs.SPISTS.bit.INT_FLAG != 1);  is takeing 9.2 us for changing the flag status.  delay_vd(1);   is taking 11.2us

As per the datasheet delay function is not required, But in pratical If the delay 11.2 us is removed, then data is corrupting.
Following is the slave code.
 

void spi_ReceiverA_Isr_vd(void)
{
  SpiaRegs.SPITXBUF = msgTxPtrSPIA_u16a[spiTxIndex_u16];
  spiTxIndex_u16++;
  if(spiTxIndex_u16 == txlen_u16)
  {
    //data transmission completed.
  }

  EALLOW;
  PieCtrlRegs.PIEACK.all|=PIEACK_GROUP6;          // Issue PIE ACK
  EDIS;
}

SPI is configured in 10Mbps speed, 512 bytes of data will be requested by master from slave on very 75ms.

 Please give suggestion for changes.

  • 0
    Mastermind 7675 points
    here www.ti.com/.../controlsuite you'll find some examples code for your processor.
    Gastón
  • 0 in reply to Gaston_Melo_Arg
    Prodigy 150 points
    Hi Gaston MeloAbove code is taken from control suite only.
    Control suit code is having loopback, but the hardware which I am using is having two saperate controllers, each controller is placed on two different PCB boards. these two controllers are connected on SPI, with cables.(Cable length is unknown).
    Thanks and RegardsRajesh
  • 0 in reply to J rajesh
    Mastermind 7675 points
    the loopback is just the configuration of one register. By disabling this bit you may test the code. Read the pdf for more info.
  • 0 in reply to Gaston_Melo_Arg
    Prodigy 150 points
    I have tested by disabling the loopback. following is the configuration for SPI in Master mode.
    void SpiAInitComm_vd(void){ SpiA_InitGpio_vd(); //clear SPI Software reset bit
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;
    //data out on Rising edge and data is latched on Falling edge
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; //SPI loopback mode disabled
    SpiaRegs.SPICCR.bit.SPILBK = 0; // loop back mode disable
    // 8 number of bits to be shifted in or out as a single character during one shift sequence
    SpiaRegs.SPICCR.bit.SPICHAR = 0xF; //Normal SPI clocking scheme
    SpiaRegs.SPICTL.bit.CLK_PHASE = 0; //Disable RECEIVER OVERRUN Flag
    SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0; //SPI configured as a master
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
    //Enables transmission For the 4-pin option SpiaRegs.SPICTL.bit.TALK = 1;
    //SPI Interrupt Disable SpiaRegs.SPICTL.bit.SPIINTENA = 0;
    // Set Baudrate = LSPCLK/ (SPIBRR +1) = 50Mhz/(0x31 + 0x1) = 1MHz
    //SpiaRegs.SPIBRR = 0x31; //for 1 Mhz //SpiaRegs.SPIBRR = 0x18; //for 2 Mhz
    SpiaRegs.SPIBRR = 0x4; //for 10 Mhz //SpiaRegs.SPIBRR = 0x2; //for 12 Mhz
    // continue SPI operation regardless of suspend or when the suspend occurred
    SpiaRegs.SPIPRI.bit.FREE = 1; //Set SPI Software reset bit
    SpiaRegs.SPICCR.bit.SPISWRESET = 1;}
  • 0 in reply to J rajesh
    Mastermind 7675 points
    quick questions:
    1) the loopback test works in differents boards??
    2) Did you read the pdf for this peripheral?
    Gastón
  • 0 in reply to Gaston_Melo_Arg
    Prodigy 150 points
    Gaston,1. Yes loop back works in different boards(both Master and slave).
    2. After reading entire datasheet I have started my work.
    In my first post, I clearly said that there is no need of delay function, but in practical with out delay only some words are received to master.
    Rajesh
  • 0 in reply to J rajesh
    Mastermind 7675 points
    www.ti.com/.../technicaldocuments some pdf you may need. Check the SPI pdf.
    Gastón
  • 0 in reply to J rajesh
    Guru 30330 points
    Rajesh,

    What is the smallest delay required to make the SPI work without issue? Can you replace the "delay_vd(1)" with a simple for loop? you can initially set it to 11.2us as it currently stands and then decrease until the SPI transmissions start failing. It is possible that the time in between sending the command from the master, your slave has not had enough time to load the next word, thus missing a word.

    Also, have you considered setting up the FIFOs on the Slave side? You can pre-load the TX Buffer and then interrupt when the FIFO is less than some threshold value. In transmit FIFO mode, the next word will automatically be loaded into the SPITXBUF after the previous word has completed. You could also set up the RXFIFO to interrupt at 16 words, noting the end of the transmission.

    -Mark
  • 0 in reply to Mark Labbato
    Guru 30330 points
    Rajesh,

    Have you resolved your issue? If so, please post your solution and verify an answer that may have helped.

    Thanks,
    Mark