SCI Receive Interrupt doesn't Occur (Bytes receives but interrupt doesn't occur)

In normal mode (not debug mode), SCI Rx interrupt doesn't occur completely..
I am really confused..

I recognized something, and my question changed little bit.

i said that above "After some time, SCI Rx interrupt begins to occur spontaneously .."
I realize that interrupt occurs not spontaneously.

I reset SCI when any error detected..

if(SciaRegs.SCIRXST.bit.RXERROR){
SciaRegs.SCICTL1.bit.SWRESET=0; // Reset active low.
SciaRegs.SCICTL1.bit.SWRESET=1;
}

BUT NOW MY PROBLEM IS :
MY SCI WORKS IN DEBUG MODE, BUT DOESNT WORK WHEN NOT DEBUG MODE.

What's the problem with this issue? I need your help,

Mehmet,

have you downloaded controlSuite? Maybe you can compare your code with the controlSuite example 'scia_loopback_interrupts'. I guess your software does not read the receiver buffer in time so that an overrun error occurs.

If you debug your software then the receiver interrupt routine should occur with every character you send via hyperterminal.

Best regards,

Karlheinz

Thanks for your reply Mr.Karlheinz.

I have controlSuite. I examine scia_loopback_interrupts. and write my codes via this example.

I read the receiver buffer in SCI RX ISR.

When i debug my software, i see that characters which i send them via hyperterminal (View->Register->SCIAREGS->SCIRXBUFF)
BUT UNFORTUNATELY RECEIVER INTERRUPT DOESN'T OCCUR..

Then i fix this problem restarting SCI, when overrun error detect with code below

if(SciaRegs.SCIRXST.bit.RXERROR){
SciaRegs.SCICTL1.bit.SWRESET=0; // Reset active low.
SciaRegs.SCICTL1.bit.SWRESET=1;
}
( But i think this way is not a good way. There must be another solution wtih this problem


now, i have new problem.
My code works good in debug mode, but it doesnt work in release mode? Can you help me about that issue?

Hard to tell from here where the problem is. I can give you only some hints where you can look.

Please be sure that your interrupts interrupts are enabled and the connection to the rx interrrupt routine is there:

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
   EALLOW;  // This is needed to write to EALLOW protected registers
   PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
   PieVectTable.SCITXINTA = &sciaTxFifoIsr;
   EDIS;   // This is needed to disable write to EALLOW protected registers

// Enable interrupts required for this example
   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER9.bit.INTx1=1;     // PIE Group 9, INT1
   PieCtrlRegs.PIEIER9.bit.INTx2=1;     // PIE Group 9, INT2
   IER = 0x100; // Enable CPU INT
   EINT;

Please check the SCIRegs as well:

  SciaRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                  // No parity,8 char bits,
                                  // async mode, idle-line protocol
   SciaRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
                                  // Disable RX ERR, SLEEP, TXWAKE
   SciaRegs.SCICTL2.bit.TXINTENA =1;
   SciaRegs.SCICTL2.bit.RXBKINTENA =1;
   SciaRegs.SCIHBAUD = 0x0000;
   SciaRegs.SCILBAUD = SCI_PRD;
   SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
   SciaRegs.SCIFFTX.all=0xC022;
   SciaRegs.SCIFFRX.all=0x0022;
   SciaRegs.SCIFFCT.all=0x00;

   SciaRegs.SCICTL1.all =0x0023;     // Relinquish SCI from Reset
   SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
   SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

Please compare your application with the SCI data sheet. Do you need rx and tx fifo? Do you need a different fifo level for the interrupt?

Restarting the SCI is good but it should only be used if a real error is there. You´ve got the problem that your rx data overruns, this must be solved.

I don't need rx-tx fifo. My configurations already same as your code above.
If i can fix these problems, i will write here.

Best regards Mr.Karlheinz,

Mehmet,

just to be sure. I saw in the other post that the boot mode pins are set now correctly. Does this also solve the Receive SCI problem?