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Hi everyone,
I want to share multiple arrays in the CPU1 and CPU2.
What do I need to do to link the address in each CPU ?
Now, I use follow the example.
C:\ti\controlSUITE\device_support\F2837xD\v180\F2837xD_examples_Dual\RAM_management
I want to add an array to this exapmle and share the address in each CPU.
My idea is separated section of the memory for each array.
As described below.
Do you have any other idea?
--------------
Linker
MEMORY
{
/* RAMGS0 : origin = 0x00C000, length = 0x001000 */
RAMGS0_0 : origin = 0x00C000, length = 0x000100
RAMGS0_1 : origin = 0x00C100, length = 0x000100
RAMGS0_2 : origin = 0x00C200, length = 0x000100
RAMGS0_3 : origin = 0x00C300, length = 0x000100
RAMGS0_4 : origin = 0x00C400, length = 0x000100
}
SECTIONS
{
SHARERAMGS0_0 : > RAMGS0_0, PAGE = 1
SHARERAMGS0_1 : > RAMGS0_1, PAGE = 1
SHARERAMGS0_2 : > RAMGS0_2, PAGE = 1
SHARERAMGS0_3 : > RAMGS0_3, PAGE = 1
SHARERAMGS0_4 : > RAMGS0_4, PAGE = 1
}
---------------
C souce
uint16_t c1_r_array_0[256]; // mapped to GS0 of shared RAM owned by CPU02
uint16_t c1_r_array_1[256]; // mapped to GS0 of shared RAM owned by CPU02
uint16_t c1_r_array_2[256]; // mapped to GS0 of shared RAM owned by CPU02
uint16_t c1_r_array_3[256]; // mapped to GS0 of shared RAM owned by CPU02
uint16_t c1_r_array_4[256]; // mapped to GS0 of shared RAM owned by CPU02
#pragma DATA_SECTION(c1_r_array_0,"SHARERAMGS0_0");
#pragma DATA_SECTION(c1_r_array_1,"SHARERAMGS0_1");
#pragma DATA_SECTION(c1_r_array_2,"SHARERAMGS0_2");
#pragma DATA_SECTION(c1_r_array_3,"SHARERAMGS0_3");
#pragma DATA_SECTION(c1_r_array_4,"SHARERAMGS0_4");
Best regards,
Mino.M
Hi,
You have defined/linked the arrays correctly. You must be aware of this but just want mention it here that when a GSRAM block is owned by CPUx, only CPUx will have write access to it. CPUy will not have write access to it (it'll have read access only).
Regards,
Vivek Singh
Vivek Singh said:Hi,
You have defined/linked the arrays correctly. You must be aware of this but just want mention it here that when a GSRAM block is owned by CPUx, only CPUx will have write access to it. CPUy will not have write access to it (it'll have read access only).
Regards,
Vivek Singh
Thank you for your reply.
I'll be careful of that.
My linker setting becomes hard When the array is increased.
Is there better idea?
Is my setting method the easiest ?
Best regards,
Mino.M