• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 82 subscribers
  • Views 1254 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

emif1 16-bit SDRAM interface with F28377D CPU1 and CPU2 - shared memory access from both the cores

Aditya BG
Expert 1825 points
Other Parts Discussed in Thread: CONTROLSUITE

Hi,

Let me know anyone has worked on emif1 16-bit SDRAM interface with F28377D for Core 1 & core 2 (CPU1 & CPU2). I'm  not finding example code for 16-bit SDRAM interface with F28377D of CPU1 & CPU2 (Dual Core). In controlsuite folder, I can find example code for CPU1 only.

Please help me , how can I access shared  SDRAM memory location from both the cores during run time. (same memory area from both the cores like shared memory access)

Thanks

Aditya

  • 0
    TI__Guru** 113875 points

    Hi Aditya,

    You want to share EMIF1 SDRAM between both CPU for READ access only or for WRITE as well. If only READ then you can do the same without any additional configuration. After CPU1 finishes the EMIF1 configuration, CPU1 as well as CPU2 (or their respective DMA) can start reading the content from SDRAM.

    For WRITE access, CPU need to take the ownership of EMIF1 by changing the value of MSEL_EMIF1 bit field in EMIF1MSEL register.

    We don't have example in cotrolSUITE for this yet. We'll plan to release one in future controlSUITE release.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1825 points

    Thank you Vivek.

    I need CPU2 as read access only. Now i have one more query.

    So whether i can use RAM management example code (sharing memory location between Two CPU's) for SDRAM too?

    I mean-

    CPU1 can read and write a message (buffer of 10MB approx) from SDRAM address. Then the same message (Same SDRAM location) can read from CPU2 ?

    Note: Currently SDRAM interface with F28377D hardware design is in progress. So i do not have hardware to test it now and i will get it by mid of July 2015.

    Thanks

    Aditya

  • 0 in reply to Aditya BG
    TI__Guru** 113875 points

    Aditya,

    CPU1 can read and write a message (buffer of 10MB approx) from SDRAM address. Then the same message (Same SDRAM location) can read from CPU2 ?

    Yes, this will work.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 113875 points

    Aditya,

    We also have following app note on accessing the SDRAM.

    http://www.ti.com/lit/an/spraby4/spraby4.pdf

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1825 points
    Thank you Vivek.
  • 0 in reply to Vivek Singh
    Expert 1825 points
    Hi Vivek,

    I'm trying that CPU2 to take ownership of emif1 by changing the value of MSEL_EMIF1 bit field in EMIF1MSEL register. But it is not getting updated. below code is used.

    EALLOW;
    Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE72;
    EDIS;

    Using debugging mode, i have monitored the register. The register Emif1ConfigRegs.EMIF1MSEL.all is not changing from 0x01 to 0x02.
    I need to read write access for CPU1 & CPU2 during run time.

    Please suggest me how CPU2 can take emif1 ownership. If you have any example code, please share with me.

    Thanks
    Aditya
  • 0 in reply to Aditya BG
    TI__Guru** 113875 points

    Aditya,

    I'm trying that CPU2 to take ownership of emif1 by changing the value of MSEL_EMIF1 bit field in EMIF1MSEL register. But it is not getting updated. below code is used.

    EALLOW;
    Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE72;
    EDIS;

    You are executing this code from CPU1 or CPU2 ? This need to be executed from CPU2 and also make sure the value of MSEL_EMIF1 is 0x0 or 0x3 (not 0x1) because only in that case CPU2 will be able to change the value to 0x2.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1825 points
    Thanks Vivek. Now its working.

    Earlier, i was not making MSEL_EMIF1 value to 0 or 3 while executing Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE72.