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Debug dual core TI-RTOS project with F28377D

Other Parts Discussed in Thread: CONTROLSUITE, TMS320F28377D

Hello,

I an trying to do a motor control project with F28377D and TI-RTOS. I have went through the TI-RTOS workshop on line and trying to build a test project on this chip to have each of the cores blink a led on the board in BIOS. My program works properly after I download it to flash and power cycle the board. But I simplily cannot have the cores boot properly in the debuger. I have found this post https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/350359 and trying to follow the answer in it and it simplily would not work for me. So I have the following questions:

1. How to connect and debug dual core TI-RTOS project with F28377D, how to boot the cores, should I select boot form RAM or Flash in the gel file menu or which reset should I use?

2. Is there a way to automate the process of connect to both core, load the program, boot the cores properly in CCS? If I need a .js file, is there a good document on how to write such a file for my need?

Thanks a lot.

Han

  • Han,

    please refer to the dual core blinky example in controlSuite for your device (C:\ti\controlSUITE\device_support\F2837xD\v180\F2837xD_examples_Dual\blinky_dc). Once you import the project into CCS and look at the build configurations you will have a FLASH_DEBUG option which should let you do what you want.

    when you select FLASH_DEBUG on CPU1 project, you will have to select FLASH build on CPU2 project (or you can do RAM builds on both the projects). Once you get both the projects programmed, reset and run CPU2, so that it is running CPU2 boot ROM and restart to the CPU1 application main() on CPU1 and step through the code. Before resetting CPU2 and after programming CPU2 application, you can set a break point on main() in CPU2 as well.

    For #2> please file a separate forum question into the compilers forum. Or I can move this question over there once we are done with #1.

    Hope this helps.

    Best Regards

    Santosh Athuru

  • forgot to mention that when you reset and run CPU2, to run CPU2 boot ROM it will hit an ESTOP0 becuase you ran boot ROM with emulator connected. Please hit run one more time, so CPU2 boot ROM will be running now waiting for boot mode IPC commands from CPU1 application.

    You can put break points at CPU2 applicaiton when you hit the ESTOP0 in boot ROM as well.

    Best Regards
    Santosh Ahturu
  • Santosh,

    Thanks a lot for your fast response and detailed suggestion. I followed your suggestion and tried to run the example in controlsuite. Then I used the similar way on my BIOS project and it did made it to work on debugging them. Here is the way I do it: with the "Enable boot form flash" and "Enable boot of the CPU 2" enabled on CPU 1 and "Enable boot form flash" enabled on CPU 2, I can start the dual CPU debug in the following order:

    Reset CPU 1
    Restart CPU 1 and get into main()
    Reset CPU 2
    Restart CPU 2 and get into main()
    Run CPU 2
    Run CPU 1

    This way, I can start debug the dual core project. I am not sure if my way of doing it is correct since this is a little bit different from what you suggested since I can only make it to work when I use the restart after the reset of each core. 

    In addition, I figured a difference between the debug and run form power cycle: The two CPU starts at the same time (at least as I can tell since the two LEDs are blinking synchronously), however, in the restart case, it seems that the CPU 2 lags CPU 1 a little bit when booting.

    I also have the following questions:

    Since the IPC message form CPU 1 to let CPU 2 boot is in the bootloader, it seems some mechanism is built into the BIOS_Start function that let CPU 2 to wait for CPU 1 to let it run since it also freeze even I start run from main (where I believe it already passed the bootloader phase).

    So when did BIOS really fire the IPC signal to boot CPU 2 in its boot up sequence, and when will CPU 2 really freeze and wait for the signal in its boot up sequence?

    Also is there a way to use the true mechanism in the boot loader to sync the two cores (which I assume your method should do, however, I could not make it to work)?

    In the attachment is a achieve of my test projects for your information in case I might made some mistakes in the configuration. Thank you very much again.

    Han

  • Han Zhang2 said:

    I also have the following questions:

    Since the IPC message form CPU 1 to let CPU 2 boot is in the bootloader, it seems some mechanism is built into the BIOS_Start function that let CPU 2 to wait for CPU 1 to let it run since it also freeze even I start run from main (where I believe it already passed the bootloader phase).

    So when did BIOS really fire the IPC signal to boot CPU 2 in its boot up sequence, and when will CPU 2 really freeze and wait for the signal in its boot up sequence?

    Also is there a way to use the true mechanism in the boot loader to sync the two cores (which I assume your method should do, however, I could not make it to work)?

    Han,

    one above...

    #1, #2> I believe the Bios_Start from CPU1 application will be sending the boot mode IPC command to CPU2. Please post question in the RTOS forums for more details.

    #3> the ROM bootloader on CPU2 will initialize the system and wait for boot mode IPC command from CPU1 application. This is documented in the ROM chapter of the device TRM.

    Hope this helps.

    Best Regards

    Santosh

  • Hi Han

    I am working on getting F28377D processor to work with both the cores. I have gone through your description and I tried the same but for some reason, the code i am trying to load works fine with individual cores but when i have both the cores loaded, the processors doesnt boot up.

    I have the code attached and if you can have a look and let me know if feedback, i greatly appreciate your concern.

    I have swi28_TMS320F28377D loaded on CPU-1, task28_TMS320F28377D on cpu-2task28_TMS320F28377D.zip

    thnaks

    Ramswi28_TMS320F28377D.zip

  • Rambabu,

    When I look at your cfg files, I figured you have "config pll and cpu clock dividers" enabled in both projects. The PLL can only be config with CPU 1, and should not be config with CPU 2. You can disable it on CPU 2 and try. Thanks.

    Han

  • Hi Han,

    Thanks for your prompt response.
    When I disable the "config pll", the cpu-2 clock is setting to default clk of 5 MHz. I dont know how to have a work around for this. I want both CPU-1 and CPU-2 to be at 190 Mhz.

    Thanks
    Ram
  • Ram,

    The main PLL can only be configured from CPU1. This will provide the CPU clock to both CPU1 and CPU2.

    See "Figure 2-5 Clocking System" of the F28377D TRM here: www.ti.com/.../spruhm8e.pdf . The entire Clocking Section in the TRM discusses the all of clock domains in detail.

    -Mark
  • Ram,

    Once you unchecked the "config pll and cpu clock dividers" without changing any numbers and seeings in that section, the CPU clock that BIOS thinks will remain the same. But be aware the default clock source of the chip is a internal oscillator which is only 10 MHz, in order to use the external oscillator, you should modify it at start up phase of BIOS in CPU 1. You can refer to my project. Thanks.

    Han

  • Han
    Can you please upload your project?
  • Ram,

    Here is a archive of my project. I thought I uploaded my project in a post earlier, which I forgot to do so.

    Han

    BIOS_DUAL_CORE_Blink.zip

  • Hi Han

    My controller is up and running now. Thanks a lot for your support.