Hello. I think a similar question was already discussed but not in as much detail as it would deserve.
We are designing a board that makes use of concerto F28M36P63C2ZWTT and we are facing a dilemma on what to do with Concerto's power supply pins. The F28M36x controlCARD (sch. v1.1 = latest) suggests a very strange PDN that, according to the modern practice, I think it doesn't sound right. Here you see (F28M36x controlCARD schematic attached) that:
a) On area 1 (VDD12.x and VDD18.x pins), controlCARD uses only one power pin, the rest are isolated from the former and connected to individual decoupling capacitors. I think that, even in the case of enabling of the internal regulator, the suggested layout is suboptimal: instead of so many discrete capacitor connections, it would be much easier to connect, e.g. the VDD12.x Concerto pins to a single area fill that is directly connected to VDD_1V2 (while, of course, keeping the number of decoupling capacitors). This would have the additional benefit of lower connection inductance for all these capacitors (plane spread inductance instead of plain tracks).
b) On area 2 (VDDIO.x pins) , controlCARD splits the power pins into 8 groups, via ferrite beads. However, according to latest literature, this practice (i.e. the isolation of noisy loads) not only degrades PDN performance due to under-damping effects but it also does not make an improvement elsewhere since only the sensitive subcircuits need to be isolated (and not the noisy ones). Again I think it would be more effective, from the power integrity point of view, to use a signle area fill on all VDDIO pins, and entirely omit the ferrite beads (or, at least, keep only one of them for connecting VDD_3V3 to the aforementioned area fill).
In any case, I would be grateful to hear your suggestions on the matter.
Best regards,
Dimitrios