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SM320F2812 - How much slower to execute CODE from external MRAM (50ns RA) than using the internal pipelined flash?

MIKAEL ANDERSSON
Prodigy 110 points

Other Parts Discussed in Thread: SM320F2812

Hi,

We are using the SM320F2812 DSP 1.8V CORE BGA179 

How much slower would an MRAM (50n read access time) connected to the external bus interface be vs using pipelined internal flash? 
The SW Engineer says about 6 times slower with the MRAM when used as CODE memory vs internal Flash used as CODE memory. 
What could be expexted ? We use a 40MHz external oscillator 
We use the internal PLL to take that up to 80Mhz 
These are the configuration parameter we use .. 

X2TIMING 0 Timing values are scaled 1:1
XSIZE 11 No other value supported
READYMODE 1 XREADY input is asynchronous
USEREADY 0 XREADY input is ignored
XRDLEAD 01 LR = 1 x 1 x 25 = 25 ns
XRDACTIVE 001 AR = (1 x 1 + 1) x 25 = 50 ns
XRDTRAIL 01 TR = 1 x 1 x 25 = 25 ns
XWRLEAD 01 LW = 1 x 1 x 25 = 25 ns
XWRACTIVE 000 AW = (1 x 0 + 1) x 25 = 25 ns
XWRTRAIL 01 TW = 1 x 1 x 25 = 25 ns

/Mikael

  • 0
    TI__Guru**** 221687 points
    Moving to the C2000 forum.

    Regards,
    Ryan
  • 0
    TI__Guru 61235 points

    Mikael,

    Your software engineer is pretty close.

    I'm not quite following why your XINTF calculations are showing a 25 ns clock.  If you have the device running at 80 MHz, then the XINTF can be run at 80 MHz clock (12.5 ns).  But I'll assume you checked the MRAM device timing specs you plan to use and concluded the setup you cite is what you want (although I question if you need the trail cycles on read.  I haven't seen devices that need this, for reads).  For a read, it will take you 100 ns (your XRDLEAD + XRDACTIVE + XRDTRAIL = 25 ns + 50 ns + 25 ns).  This is 8 cycles, to access 16 bits of data.

    Most instructions are 16 bits, so basically you're going to execute 1 instruction every 8 cycles.  Effective XINTF instruction performance at 80 MHz will therefore be 10 MIPS.  Throw in some 32 bit instructions, and things will get even worse.  Maybe you get 8 MIPS from the XINTF.  The problem here is this "MRAM" chip with 50 ns access time.  If you used a fast ASRAM with 10 or 12 ns SRAM, things would be much better.

    At 80 MHz, the flash memory will give effective performance of 80 MIPS.  There is a flash pipeline that fetches 64 bits per access.  At 80 MHz, the flash needs 3 cycles per access.  So you will effectively fetch 64 bits every 3 cycles.  Most instructions are 16 bits, so let's just consider the 16 bit instructions.  You will get 4 instructions every 3 cycles, but it will take you 4 cycles to execute these.  Effective flash performance will therefore be 1 instructions per cycle (in other words, the flash pipeline will keep the execution pipeline sufficiently fed).  Even if there were some 32 bit instructions thrown in, at 80 MHz you still have some margin (because the flash access is 3 cycles, and you fetch 64 bits of instruction, so if you had a 32 bitter in there, it would not degrade the performance).  So we can state that effective flash performance at 80 MHz is about 80 MIPS.

    Regards,

    David