TMS320F28075 HRPWM period mode

Kengo Furuya

Other Parts Discussed in Thread: TMS320F28075

Hi Champ,

My customer is using TMS320F28075 HRPWM master with period mode.

In this case, they see the some jitter on PWM output when they set ZRO or PRD to AQCTLA/B. And they does not see the jitter when they set CAU/CAD to AQCTLA/B.

The user should not set ZRO or PRD to AQCTLA/B to avoid to generate the jitter on PWM output?

If additional condition or setting to avoid the jitter, could you please let me know it?

Regards,

Furuya

over 9 years ago

0 Kengo Furuya over 9 years ago

TI__Expert 7650 points

Sorry, I found Figure 14-10. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) in TRM, and I understood user should avoid the action at ZRO and PRD.

Let me ask about the following NOTE in TRM 14.2.4.4.1 High-Resolution Period Configuration.

NOTE:
When high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1 - 2 cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count mode). For this reason, TBCTL[SYNCOSEL] should not be set to 1 (CTR = 0 is EPWMxSYNCO source) or 2 (CTR = CMPB is EPWMxSYNCO source). Otherwise, the jitter will occur on every PWM cycle with the synchronization pulse.

In my understanding, only the slave PWM module has some jitter caused by EPWMxSYNC singal, so the master PWM module has no jitter because the master PWM module does not have SYNC signal from anywhere. Is that correct?

Regards,
Furuya

0 Subrahmanya over 9 years ago in reply to Kengo Furuya

TI__Mastermind 24095 points

Hi Furuya,

Your understanding is correct. The SYNC related jitter is to the slave receiving the SYNC.
There is no impact on the Master generating the sync pulse.

-Bharathi

0 Kengo Furuya over 9 years ago in reply to Subrahmanya

TI__Expert 7650 points

Hi Bharathi,

Let me ask again. Now customer see the jitter on PWM pulse when they use the attached code.

8461.hrpwm_updown_count_sfo_v8.c

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/********************************************************************************
 * FILE:    hrpwm_updown_count_sfo_v8.c
 *
 * TITLE:   F2807x Device HRPWM SFO V8 High-Resolution Dead Band
 *          (up-down count) example
 *
 * ASSUMPTIONS:
 *
 * This program requires the F2807x header files, including the
 * following files required for this example:
 * SFO_V8.h and SFO_v8_fpu_lib_build_c28.lib
 *
 * Monitor ePWM1 & ePWM2 A/B pins on an oscilloscope
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

/********************************************************************************
 * FILE:	hrpwm_updown_count_sfo_v8.c
 *
 * TITLE:	F2807x Device HRPWM SFO V8 High-Resolution Dead Band
 * 			(up-down count) example
 *
 * ASSUMPTIONS:
 *
 * This program requires the F2807x header files, including the
 * following files required for this example:
 * SFO_V8.h and SFO_v8_fpu_lib_build_c28.lib
 *
 * Monitor ePWM1 & ePWM2 A/B pins on an oscilloscope
 *
 * DESCRIPTION:
 *
 * This example sweeps the ePWM frequency while trying to maintain
 * a duty cycle of ~50% in ePWM up count mode. In addition, this
 * example demonstrates ePWM high-resolution dead band (HRDB)
 * capabilities utilizing the HRPWM extension of the respective
 * ePWM module.
 *
 * This example calls the following TI's micro-edge positioner (MEP)
 * Scale Factor Optimizer (SFO) software library V8 functions:
 *
 * SFO();
 *
 * which updates MEP_ScaleFactor value
 * - returns 0 if not complete for the specified channel
 * - returns 1 when complete for the specified channel
 * - returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255
 *   (Auto-conversion may not function properly under this condition)
 *
 * This example is intended to demonstrate the HRPWM capability to control
 * the dead band falling edge delay (FED) and rising edge delay (RED). This
 * code can be optimized for code efficiency.
 *
 * ePWM1 and ePWM2 A/B channels will have fine edge movement due to HRPWM
 * control
 *
 * =======================================================================
 * NOTE: For more information on using the SFO software library, see the
 * F2807x High-Resolution Pulse Width Modulator (HRPWM) Reference Guide
 * =======================================================================
 *
 * To load and run this example:
 * --**!!IMPORTANT!!** - in SFO_V8.h, set PWM_CH to the max number of
 *   HRPWM channels plus one. For example, for the F2807x, the
 *   maximum number of HRPWM channels is 8. 8+1=9, so set
 *   #define PWM_CH 9 in SFO_V8.h. (Default is 8)
 * --Run this example at maximum SYSCLKOUT
 * --Activate Real time mode
 * --Run the "AddWatchWindowVars_HRPWM.js" script from the scripting console
 *   (View -> Scripting Console) to populate watch window
 * --Run the code
 * --Watch ePWM A / B channel waveforms on a Oscilloscope
 * --In the watch window:
 * 	 Change the variable InputPeriodInc to increase or decrease the frequency
 * 	 sweep rate. Setting InputPeriodInc = 0 will stop the sweep while allowing
 * 	 other variables to be manipulated and updated in real time.
 * --In the watch window:
 *   Change values for registers EPwm1Regs.DBRED/EPwm2Regs.DBRED to see changes
 *   in rising edge dead bands for ePWM1 and ePWM2 respectively. Alternatively,
 *   changing values for registers EPwm1Regs.DBFED/EPwm2Regs.DBFED will change
 *   falling edge dead bands for ePWM1 and ePWM2. Changing these values will
 *   alter the duty cycle percentage for their respective ePWM modules.
 *   **!!NOTE!!** - DBRED/DBFED values should never be set below DBRED/DBFED = 4.
 *   				Do not set these values to 0, 1, 2 or 3.
 * --In the watch window:
 *   Change values for registers EPwm1Regs.DBREDHR.bit.DBREDHR/EPwm2Regs.DBREDHR.bit.DBREDHR
 *   to increase or decrease number of resolvable high-resolution steps at the
 *   dead band rising edge. Alternatively, change values for
 *   EPwm1Regs.DBFEDHR.bit.DBFEDHR/EPwm2Regs.DBFEDHR.bit.DBFEDHR to change the
 *   number of resolvable steps at the dead band falling edge for ePWM1 and ePWM2
 *   respectively.
 *
 *********************************************************************************
 * $TI Release: F2807x Support Library v160 $
 * $Release Date: Wed Aug 5 13:52:00 CDT 2015 $
 * $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
 *             http://www.ti.com/ ALL RIGHTS RESERVED $
 *********************************************************************************/

#include "F28x_Project.h"     // Device Headerfile and Examples Include File
#include "F2807x_struct.h"
#include "SFO_V8.h"

//define # of PWM channels (F2807x)
#define	PWM_CH	 	  		9

// To switch between HR and non-HR behavior just change '#define With_HR' value (0 or 1)
#define With_HR				1

// Declare your function prototypes here
//---------------------------------------------------------------
void HRPWM1_Config(int);
void HRPWM2_Config(int);
void FreqCtl_func(void);			// frequency modulation & phase sync function
interrupt void PRDEQfix_ISR(void);	// PRD_EQ translator calculations
void error(void);

// Global variables
volatile struct 	EPWM_REGS 	*ePWM[PWM_CH + 1]; 		// vars for flags
int MEP_ScaleFactor;

// General System variables
Uint16 UpdateFine, PeriodFine, status;
Uint16 *EPWM1_TRREM, *EPWM2_TRREM;
Uint16 temp_REM2 = 0, temp_PHS2, PhaseFine2;
Uint32 CountUpdatefine = 0, CountUpdateMax = 0;
Uint16 Period = 0, PeriodFine = 0, period_odd = 0;
Uint16 PeriodIncrement = 0, PeriodFineIncrement = 0;
Uint32 InputPeriodInc = 0;
Uint32 PeriodFine_temp = 0;
Uint16 PWM_first = 1;
Uint16 PWM_second = 2;

Uint16	Period_max = 600, Period_min = 360;

void main(void)
{  
	InitSysCtrl();

    EALLOW;
    ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 1;
    EDIS;

    // Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
	DINT;

    // Initialize the PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F28M36x_PieCtrl.c file.
	InitPieCtrl();

    // Disable CPU interrupts and clear all CPU interrupt flags:
	IER = 0x0000;
	IFR = 0x0000;

    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in F28M36x_DefaultIsr.c.
    // This function is found in F28M36x_PieVect.c.
	InitPieVectTable();

	// Set address of ISR in PIE vector table
	EALLOW;
	PieVectTable.EPWM1_INT = &PRDEQfix_ISR;
	EDIS;

	// Calling SFO() updates the HRMSTEP register with calibrated MEP_ScaleFactor.
	// HRMSTEP must be populated with a scale factor value prior to enabling
	// high resolution period control.
    status = SFO_INCOMPLETE;
    while  (status== SFO_INCOMPLETE) {  // Call until complete
        status = SFO();
        if (status == SFO_ERROR) {
            error();
        }
    }

    EPWM1_TRREM = (Uint16 *) 0x402E;
    EPWM2_TRREM = (Uint16 *) 0x412E;

	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
	EDIS;

	// Init HRPWM1/HRPWM2
	InitEPwm1Gpio();
	InitEPwm2Gpio();
	HRPWM1_Config(360);
	HRPWM2_Config(360);
//	HRPWM1_Config(0x96);	//150
//	HRPWM2_Config(0x96);

	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;			//resync PWM timebase clock
	(*EPWM[PWM_first]).GLDCTL2.bit.OSHTLD = 1;		// This should also write to GLDCTL2 of PWM2
	EDIS;

	// configure ePWM1 to generate interrupts on period match
	(*EPWM[PWM_first]).ETSEL.bit.INTSEL = 1;		// interrupt on counter zero match
	(*EPWM[PWM_first]).ETSEL.bit.INTEN = 1;			// enable peripheral interrupt
	(*EPWM[PWM_first]).ETPS.bit.INTPRD = 1;			// generate interrupt on every event
	PieCtrlRegs.PIEIER3.bit.INTx1 = 1;				// enable ePWM1 interrupt in PIE

	IER |= 0x0004;									// enable core INT #3
	EINT;											// clear global interrupt mask

	UpdateFine = 0; 								//disable continuous updates
	Period = 360;
	PeriodFine = 0x0;
	CountUpdateMax = 0x0FFFF;
	CountUpdatefine = CountUpdateMax;

	//watch window variable
	InputPeriodInc = 6553;

#if 0
	for(;;)
	{
		while(UpdateFine==0)
		{
			if(CountUpdatefine>=CountUpdateMax)
			{
				if(Period<Period_max)
				{
					//perform sweep
					PeriodIncrement = InputPeriodInc >> 16;
					PeriodFineIncrement = (Uint16) InputPeriodInc;
					Period = Period+PeriodIncrement;
					PeriodFine_temp = (Uint32)PeriodFine + (Uint32)PeriodFineIncrement;
					if(PeriodFine_temp>=0x10000)
					{
						PeriodFine_temp = PeriodFine_temp-0x10000;
						Period = Period+1;
					}

					if (Period%2 == 1) // Period is odd - CMP is divide by 2 for 50% duty
						period_odd = 1;
					else period_odd = 0;

					PeriodFine = (Uint16) PeriodFine_temp;

					//update PWM values for non-zero increment
					if (InputPeriodInc !=0)
					{
						FreqCtl_func();
					}
				}
				else
				{
					Period = Period_min;
					PeriodFine = 0;
					if (InputPeriodInc != 0)
					{
						FreqCtl_func();
					}
				}
				CountUpdatefine = 0;
			}
			CountUpdatefine++;
		}
	}
#else
    for(;;)
    {
            status = SFO(); // in background, MEP calibration module continuously updates MEP_ScaleFactor
            if (status == SFO_ERROR) {
                error();   // SFO function returns 2 if an error occurs & # of MEP steps/coarse step
            }              // exceeds maximum of 255.
	}
#endif
}  

void HRPWM1_Config(period)
{
// ePWM1 register configuration with HRPWM
// ePWM1A toggle low/high with MEP control on Rising edge

	(*EPWM[PWM_first]).TBCTL.bit.PRDLD = TB_SHADOW;	        	// set Immediate load
	(*EPWM[PWM_first]).TBPRD = period;		                    // PWM frequency = 1 / period
	(*EPWM[PWM_first]).TBPRDHR = 0xBA00;	                    // PWM frequency = 1 / period
	(*EPWM[PWM_first]).CMPA.bit.CMPA = period / 2;              // set duty 50% initially
//    (*EPWM[PWM_first]).CMPA.bit.CMPAHR = (1 << 8);              // initialize HRPWM extension
    (*EPWM[PWM_first]).CMPA.bit.CMPAHR = 0x5D00;              // initialize HRPWM extension
	(*EPWM[PWM_first]).CMPB.bit.CMPB = period / 2;	            // set duty 50% initially
// 	(*EPWM[PWM_first]).CMPB.bit.CMPBHR = (1 << 8);              // initialize HRPWM extension
	(*EPWM[PWM_first]).CMPB.bit.CMPBHR = 0x5D00;              // initialize HRPWM extension
	(*EPWM[PWM_first]).TBPHS.all = 0;
	(*EPWM[PWM_first]).TBCTR = 0;

	(*EPWM[PWM_first]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	(*EPWM[PWM_first]).TBCTL.bit.PHSEN = TB_DISABLE;		       // ePWM1 is the Master
	(*EPWM[PWM_first]).TBCTL.bit.SYNCOSEL = 0x1;
	(*EPWM[PWM_first]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
	(*EPWM[PWM_first]).TBCTL.bit.CLKDIV = TB_DIV1;
//	(*EPWM[PWM_first]).TBCTL.bit.FREE_SOFT = 3;

	(*EPWM[PWM_first]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;      // LOAD CMPA on CTR = 0
	(*EPWM[PWM_first]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

	(*EPWM[PWM_first]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	(*EPWM[PWM_first]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

	(*EPWM[PWM_first]).AQCTLA.bit.CAU = AQ_SET;
	(*EPWM[PWM_first]).AQCTLA.bit.CAD = AQ_CLEAR;

	EALLOW;
#if	With_HR
	(*EPWM[PWM_first]).HRCNFG.all = 0x1353;
	(*EPWM[PWM_first]).HRPCTL.bit.HRPE = 1;                  // Turn on high-resolution period control.
	(*EPWM[PWM_first]).TBCTL.bit.SWFSYNC = 1;                // Synchronize high resolution phase to start HR period
#endif

	(*EPWM[PWM_first]).GLDCFG.bit.CMPA_CMPAHR = 1;
	(*EPWM[PWM_first]).GLDCFG.bit.CMPB_CMPBHR = 1;
	(*EPWM[PWM_first]).GLDCTL.bit.GLDMODE = 2;			  	// Load on CTR = ZERO_PRD (2) / ZERO (1)
	(*EPWM[PWM_first]).GLDCTL.bit.OSHTMODE = 1; 			// One shot mode enabled
	(*EPWM[PWM_first]).GLDCTL.bit.GLD = 1;					// Enable global load

	(*EPWM[PWM_first]).EPWMXLINK.bit.GLDCTL2LINK = PWM_first - 1;	// Writes to GLDCTL2 of PWM1 will result in simultaneous writes to GLDCTL2 of PWM2

	(*EPWM[PWM_first]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
	(*EPWM[PWM_first]).DBCTL.bit.POLSEL = DB_ACTV_HIC;
	(*EPWM[PWM_first]).DBCTL.bit.IN_MODE = DBA_ALL;
	(*EPWM[PWM_first]).DBCTL.bit.SHDWDBREDMODE = 1;
	(*EPWM[PWM_first]).DBCTL.bit.SHDWDBFEDMODE = 1;
	(*EPWM[PWM_first]).DBCTL.bit.LOADREDMODE = 0;				// Load on Counter == 0
	(*EPWM[PWM_first]).DBCTL.bit.LOADFEDMODE = 0;				// Load on Counter == 0
	(*EPWM[PWM_first]).DBCTL.bit.HALFCYCLE = 1;
	(*EPWM[PWM_first]).DBRED = 4;
	(*EPWM[PWM_first]).DBREDHR.bit.DBREDHR = 0x0;
	(*EPWM[PWM_first]).DBFED = 4;
	(*EPWM[PWM_first]).DBFEDHR.bit.DBFEDHR = 0x0;

	(*EPWM[PWM_first]).HRCNFG2.bit.EDGMODEDB = 3;        	// DBREDHR and DBFEDHR
	(*EPWM[PWM_first]).HRCNFG2.bit.CTLMODEDBRED = 0;      	// Load on ZRO
	(*EPWM[PWM_first]).HRCNFG2.bit.CTLMODEDBFED = 0;      	// Load on ZRO
	(*EPWM[PWM_first]).DBREDHR.bit.DBREDHR = 0<<9;

	EDIS;
}

void HRPWM2_Config(period)
{
// ePWM2 register configuration with HRPWM
// ePWM2A toggle low/high with MEP control on Rising edge

	(*EPWM[PWM_second]).TBCTL.bit.PRDLD = TB_SHADOW;	        	// set Immediate load
	(*EPWM[PWM_second]).TBPRD = period;		                    	// PWM frequency = 1 / period
	(*EPWM[PWM_second]).TBPRDHR = 0xBA00;	                    // PWM frequency = 1 / period
	(*EPWM[PWM_second]).CMPA.bit.CMPA = period / 2;              	// set duty 50% initially
//    (*EPWM[PWM_second]).CMPA.bit.CMPAHR = (1 << 8);              	// initialize HRPWM extension
    (*EPWM[PWM_second]).CMPA.bit.CMPAHR = 0x5D00;              // initialize HRPWM extension
	(*EPWM[PWM_second]).CMPB.bit.CMPB = period / 2;	                // set duty 50% initially
    (*EPWM[PWM_second]).CMPB.bit.CMPBHR = (1 << 8);              	// initialize HRPWM extension
	(*EPWM[PWM_second]).TBPHS.all = 0;
	(*EPWM[PWM_second]).TBCTR = 0;

	(*EPWM[PWM_second]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	(*EPWM[PWM_second]).TBCTL.bit.PHSEN = TB_DISABLE;		       // ePWM1 is the Master
	(*EPWM[PWM_second]).TBCTL.bit.SYNCOSEL = 0x0;
	(*EPWM[PWM_second]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
	(*EPWM[PWM_second]).TBCTL.bit.CLKDIV = TB_DIV1;
//	(*EPWM[PWM_second]).TBCTL.bit.FREE_SOFT = 3;

	(*EPWM[PWM_second]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;      // LOAD CMPA on CTR = 0
	(*EPWM[PWM_second]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
	(*EPWM[PWM_second]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	(*EPWM[PWM_second]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

	(*EPWM[PWM_second]).AQCTLA.bit.CAU = AQ_SET;
	(*EPWM[PWM_second]).AQCTLA.bit.CAD = AQ_CLEAR;

	EALLOW;
#if	With_HR
	(*EPWM[PWM_second]).HRCNFG.all = 0x1353;
	(*EPWM[PWM_second]).HRPCTL.bit.HRPE = 1;                  // Turn on high-resolution period control.
	(*EPWM[PWM_second]).TBCTL.bit.SWFSYNC = 1;                // Synchronize high resolution phase to start HR period
#endif


	(*EPWM[PWM_second]).TBCTL.bit.PHSDIR = 1;				// count up after SYNC event
	(*EPWM[PWM_second]).TBPHS.bit.TBPHS = 180;

	(*EPWM[PWM_second]).GLDCFG.bit.CMPA_CMPAHR = 1;
	(*EPWM[PWM_second]).GLDCFG.bit.CMPB_CMPBHR = 1;
	(*EPWM[PWM_second]).GLDCTL.bit.GLDMODE = 2;			  	// Load on CTR = ZERO_PRD (2) / ZERO (1)
	(*EPWM[PWM_second]).GLDCTL.bit.OSHTMODE = 1; 			// One shot mode enabled
	(*EPWM[PWM_second]).GLDCTL.bit.GLD = 1;					// Enable global load

	(*EPWM[PWM_second]).EPWMXLINK.bit.GLDCTL2LINK = PWM_first - 1;	// Writes to GLDCTL2 of PWM1 will result in simultaneous writes to GLDCTL2 of PWM2

	(*EPWM[PWM_second]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
	(*EPWM[PWM_second]).DBCTL.bit.POLSEL = DB_ACTV_HIC;
	(*EPWM[PWM_second]).DBCTL.bit.IN_MODE = DBA_ALL;
	(*EPWM[PWM_second]).DBCTL.bit.SHDWDBREDMODE = 1;
	(*EPWM[PWM_second]).DBCTL.bit.SHDWDBFEDMODE = 1;
	(*EPWM[PWM_second]).DBCTL.bit.LOADREDMODE = 0;				// Load on Counter == 0
	(*EPWM[PWM_second]).DBCTL.bit.LOADFEDMODE = 0;				// Load on Counter == 0
	(*EPWM[PWM_second]).DBCTL.bit.HALFCYCLE = 1;
	(*EPWM[PWM_second]).DBRED = 4;
	(*EPWM[PWM_second]).DBREDHR.bit.DBREDHR = 0x0;
	(*EPWM[PWM_second]).DBFED = 4;
	(*EPWM[PWM_second]).DBFEDHR.bit.DBFEDHR = 0x0;

	(*EPWM[PWM_second]).HRCNFG2.bit.EDGMODEDB = 3;        // DBREDHR and DBFEDHR
	(*EPWM[PWM_second]).HRCNFG2.bit.CTLMODEDBRED = 0;      // Load on ZRO
	(*EPWM[PWM_second]).HRCNFG2.bit.CTLMODEDBFED = 0;      // Load on ZRO
	(*EPWM[PWM_second]).DBREDHR.bit.DBREDHR = 0<<9;

	EDIS;
}

void FreqCtl_func()		// This function is called only if values need to be changed
{
	if (period_odd)
	{
		(*EPWM[PWM_first]).CMPA.bit.CMPAHR = (PeriodFine>>1) + 0x7FFF; 		//In Q16 format. Add 0.5 if period is odd
		(*EPWM[PWM_second]).CMPA.bit.CMPAHR = (PeriodFine>>1) + 0x7FFF; 	//In Q16 format
		(*EPWM[PWM_first]).CMPB.bit.CMPBHR = (PeriodFine>>1) + 0x7FFF; 		//In Q16 format. Add 0.5 if period is odd
		(*EPWM[PWM_second]).CMPB.bit.CMPBHR = (PeriodFine>>1) + 0x7FFF; 	//In Q16 format
	}
	else
	{
		(*EPWM[PWM_first]).CMPA.bit.CMPAHR = PeriodFine>>1; 		//In Q16 format
		(*EPWM[PWM_second]).CMPA.bit.CMPAHR = PeriodFine>>1; 		//In Q16 format
		(*EPWM[PWM_first]).CMPB.bit.CMPBHR = PeriodFine>>1; 		//In Q16 format
		(*EPWM[PWM_second]).CMPB.bit.CMPBHR = PeriodFine>>1; 		//In Q16 format
	}

	(*EPWM[PWM_first]).CMPA.bit.CMPA = (Period>>1)+1; 		//In Q16 format
	(*EPWM[PWM_second]).CMPA.bit.CMPA = (Period>>1)+1; 		//In Q16 format.
	(*EPWM[PWM_first]).CMPB.bit.CMPB = (Period>>1)+1; 		//In Q16 format
	(*EPWM[PWM_second]).CMPB.bit.CMPB = (Period>>1)+1; 		//In Q16 format

	temp_PHS2 = ((Period)>>1);

	switch(period_odd)
	{
		case 1:
			PhaseFine2 =  0xFF-(PeriodFine>>9) - 0x7F; //Accounting for divide by 2 = 0.5
			break;

		default:
			PhaseFine2 =  0xFF-(PeriodFine>>9);
			break;
	}

	temp_REM2 =  (Uint16) 0x100 + PhaseFine2; 		//No fractional phase shift to account for
	UpdateFine = 1;

}

interrupt void PRDEQfix_ISR(void)
{
	EALLOW;
	if (UpdateFine == 1)
	{
		(*EPWM[PWM_first]).GLDCTL2.bit.OSHTLD = 1;		// This should also write to GLDCTL2 of PWM2, PWM3 and PWM4

		(*EPWM[PWM_second]).TBCTL.bit.PHSEN = TB_ENABLE;        // TBCTR phase load on SYNC (required for updown count HR control
		(*EPWM[PWM_second]).TBPHS.bit.TBPHS = temp_PHS2;		// coarse phase offset relative to ePWM1
		*EPWM2_TRREM = temp_REM2;

	    (*EPWM[PWM_second]).TBPRDHR = PeriodFine; 		//In Q16 format
		(*EPWM[PWM_second]).TBPRD = Period; 			//In Q16 format

		(*EPWM[PWM_first]).TBPRDHR = PeriodFine; 		//In Q16 format
		(*EPWM[PWM_first]).TBPRD = Period; 				//In Q16 format
		*EPWM1_TRREM = 0x100;
		UpdateFine=0;
	}
	else
	{
		(*EPWM[PWM_second]).TBCTL.bit.PHSEN = TB_DISABLE;
	}
	// re-initialise for next PWM interrupt
	PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;   			// acknowledge PIE interrupt
	(*EPWM[PWM_first]).ETCLR.bit.INT = 1;				// clear interrupt bit
	EDIS;
}

void error (void) {
    ESTOP0;         // Stop here and handle error
}

//===========================================================================
// No more.
//===========================================================================

Now HRLOAD and HRLOADB is set as HR_CTR_ZERO. At this time, the jitter is generated on PWM pulse. When HRLOAD and HRLOADB is set as HR_CTR_PRD also, the jitter is there.

And, if HRLOAD and HRLOADB is changed to HR_CTR_ZERO_PRD from HR_CTR_ZERO or HR_CTR_PRD, the jitter go away from PWM pulse.

PWM module is configured as Master, so SYNC pulse timing is not related to cause the jitter.

Could you let me know the reason why the jitter is generated when I set HRLOAD and HRLOADB is set as HR_CTR_ZERO or HR_CTR_PRD?

Now I'm referring 14.2.4.4.1 High-Resolution Period Configuration in TRM. This sample is also setting HRCNFG[HRLOAD] = 2 (load on either CTR = 0 or CTR = PRD).

Is there any reason we should set HRCNFG[HRLOAD] = 2?

Regards,

Furuya

0 Subrahmanya over 9 years ago in reply to Kengo Furuya

TI__Mastermind 24095 points

Furuya,

This is expected behavior - for HR Period control mode of operation HRLOAD should always be configured to
HRCNFG[HRLOAD] = 2 (load on either CTR = 0 or CTR = PRD)

-Bharathi.

0 Kengo Furuya over 9 years ago in reply to Subrahmanya

TI__Expert 7650 points

Bharathi,

Thank you for your reply. Could you explain the reason why HRLOAD should always be configured to 2?

I understand this is the rule at HR period control mode, but I want to understand the reason from the technical point of view.

Regards,

Furuya

0 Kengo Furuya over 9 years ago in reply to Kengo Furuya

TI__Expert 7650 points

Hi Bharathi,

Can I have an answer to above question?

Regards,
Furuya

0 Subrahmanya over 9 years ago in reply to Kengo Furuya

TI__Mastermind 24095 points

Primary reason is that, in this mode there are 2 updates needed in 1 PWM cycle - on Zero and PRD.

-Bharathi.

C2000™︎ microcontrollers

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TMS320F28075 HRPWM period mode