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Hi,
I am working on implementing Manchester encoding algorithm using epwm1 on DSp TMS320F28335.
i am trying to update the EPwm1Regs.AQCTLA.bit.ZRO and EPwm1Regs.AQCTLA.bit.CAU register for every interrupt based on the value of current bit that needs to be encoded and next in line bit (following Manchester encoding) .
However, the output i see on the oscilloscope is not having the updated result. it always follows the EPwm1Regs.AQCTLA.bit.ZRO and EPwm1Regs.AQCTLA.bit.CAU register that i have defined during initialization.
I checked my code using breakpoints and the resisters in question updates as i require them to be, however the output remains the same.
here is my code for ISR and initialization,
interrupt void epwm1_isr(void)
{
if(flag==1)
{EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
EPwm1Regs.CMPA.half.CMPA = 1500;
}
if(flag==0)
{
epwm1value= nextvalue[j];
if (epwm1value == 1)
{
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.CMPA.half.CMPA = 750;
}
else
{EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.CMPA.half.CMPA = 750;
}
if(nextvalue[j]== nextvalue[j+1])
{EPwm1Regs.AQCTLA.bit.ZRO = AQ_TOGGLE;
}
else
{EPwm1Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
}
j++;
if(j>15)
{j=0;
flag=1;
}
}
EPwm1TimerIntCount++;
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 1500; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup compare
EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1B on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
// Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = 0x0;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event
}
is there something i am missing ? or can we not update the AQCTLA register during run time?