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Tool/software: Code Composer Studio
Dear TI community,
I found a strange behavior when I use shadow load for AQCTLA & AQTCLB registers. (AQCTL.bit.SHDWAQyMODE = 1)
I wan't to create a single PWM one pulse, so i config the ePWM module for normal operation, with the addition that i config the AQCTLA register to clear the A output in any case. With shadowed load this settings gets active after the first pulse (shadowed to active load when TBCTR == zero).
Here is my pwm start function:
void pfc_pwm_start( uint16_t generate_onepulse){
EALLOW;
uint16_t j;
for (j=0;j<1;j++)
{
/*
* Set Action Qualifier register for normal operation
*
* Main switch: set - counter == compare A (during up count)
* clear - counter == zero
*
* Sub switch: set - counter == compare A (during up count)
* clear - counter == compare B (during up count)
*
* Configure register first for immediate load, to make changes immediately active
*/
(*ePWM[j]).AQCTL.bit.SHDWAQAMODE = 0; // immediate load for ACTLA register
(*ePWM[j]).AQCTL.bit.SHDWAQBMODE = 0; // immediate load for ACTLB register
(*ePWM[j]).AQCTLA.bit.CAU = AQ_SET;
(*ePWM[j]).AQCTLA.bit.ZRO = AQ_CLEAR;
(*ePWM[j]).AQCTLB.bit.CAU = AQ_SET;
(*ePWM[j]).AQCTLB.bit.CBU = AQ_CLEAR;
/*
* Set Action Qualifier register for One Pulse operation - If enabled
*
* Clear both switches at all actions
*
* Configure register first for shadowed load, to make changes active after next counter reset
* -> first pulse normal operation (configuration above),
* after first pulse clear all (configuration below) -> one shot function
*/
if(generate_onepulse){
GpioDataRegs.GPASET.bit.GPIO6 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO6 = 1;
(*ePWM[j]).AQCTL.bit.SHDWAQAMODE = 1; // enable shadow load for ACTLA register
(*ePWM[j]).AQCTL.bit.SHDWAQBMODE = 1; // enable shadow load for ACTLB register
(*ePWM[j]).AQCTL.bit.LDAQASYNC = 0;
(*ePWM[j]).AQCTL.bit.LDAQBSYNC = 0;
(*ePWM[j]).AQCTLA.bit.CAU = AQ_CLEAR;
(*ePWM[j]).AQCTLA.bit.ZRO = AQ_CLEAR;
(*ePWM[j]).AQCTLB.bit.CAU = AQ_CLEAR;
(*ePWM[j]).AQCTLB.bit.CBU = AQ_CLEAR;
}
/*
* Force a one time action qualifier event to guarantee a low level for
* both switches at timer start
*/
(*ePWM[j]).AQSFRC.bit.OTSFA = 1;
(*ePWM[j]).AQSFRC.bit.OTSFB = 1;
/*
* Clear permanent trip zone low level and start timer
*/
(*ePWM[j]).TZCLR.bit.OST = 1; // clear one shot event
(*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UP; // start counter
}
EDIS;
}When I write
(*ePWM[j]).AQCTL.bit.LDAQASYNC = 1; // shadowed to active load @ LDAQAMODE (LDAQAMODE = 0) or SYNCIN event
(*ePWM[j]).AQCTL.bit.LDAQBSYNC = 1;
I will have the expected behavior (only one ePWM1A pulse CH4):
But when I write
(*ePWM[j]).AQCTL.bit.LDAQASYNC = 0; // shadowed to active load only @ LDAQAMODE (LDAQAMODE = 0)
(*ePWM[j]).AQCTL.bit.LDAQBSYNC = 0;I will have a strange behavior
In my opinion, there should be no difference between the two configurations, because shadowed to active load is in both cases @ TBCTR = zero and the DCAEVT1 will reset the TBCTR and the TBPHS register is zero! I have plot the EPWMSYNCO on CH2 for verification that a TBCTR zero event will be generated. After the first EPWMSYNCO pulse, the shadowed registers should transfered to the active registers. But in the second behavior, the active register gets never updated from the shadowed register.
Is it possible that this note causes this behavior: 
Because resetting the pin and shadowed to active load is on the same clock cycle? (TBCTR == zero)
Thank you!
I've found another inexplicable behavior:
If I write the following code, all works perfect:
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;
If I write the following (clear A & B outputs after single pulse on every event):
EPwm1Regs.AQCTLA.all = 0x555; EPwm1Regs.AQCTLB.all = 0x555;
than the pulse look like this:
So it looks like the CAU event is shadowed but the CBU event is not shadowed?
I've created a project for you to test the behavior. I've used the LAUNCHXL-F280049C board. The EPwm1 module is configured in upcount. The PWM is turned off at TBCTR == 0 and turned on at TBCTR == CAU. The CMPSS1H comparator can reset the counter, so pwm is turned off after a comparator trip or when the period value is reached.
Pleas make a connection between Pin 70 (DACA_OUT) & Pin 64 (CMP1SSH input) to simulate a current flow to with the DAC.
With the following configuration the PWM works as expected:
#define AQCTL_LDAQAMODE 1 #define AQCTLA_CLEAR_ALL 0
With this configuration the shadowed registers never updates the active register (=> no onepulse):
#define AQCTL_LDAQAMODE 0 #define AQCTLA_CLEAR_ALL 0
With this configuration CAU is shadowed and CBU not. (=> PWM on time is always 200ns, independent of the comparator trip)
#define AQCTL_LDAQAMODE 1 #define AQCTLA_CLEAR_ALL 1
Thank you for your help!
