• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 883 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28022: About SCI SWRESET

Koichi Ie
Intellectual 270 points
Part Number: TMS320F28022

Hello,

Please tell me about the timing of the sending and receiving data with a SCI SWRESET.

SciaRegs.SCICTL1.bit.SWRESET = 0;
SciaRegs.SCICTL1.bit.SWRESET = 1;
.
.
Set SWRESET to "1" when sending and receiving is possible?


Results verified with EVM

<send data>
after 1-bit data delay

<receive data>
after less than 1-bit data delay


Please tell me the time available to send and receive.

  • 0
    TI__Mastermind 42195 points

    Koichi,

    I am looking into this will update you when I know something.

    Regards,

    Cody

  • 0 in reply to Cody Watkins
    TI__Mastermind 42195 points

    Koichi,

    I can confirm your findings! For both receiving and transmitting the delay should be less than or equal to 1 bit timing. Often the RX delay is less because it is oversampled.

    Transmit delay <= 1 bit timing
    Receive delay <= 1 bit timing

    Does this answer your question? If you have more questions please ask.

    Regards,
    Cody

  • 0 in reply to Cody Watkins
    Intellectual 270 points

    Cody-san,

    Thank you for the confirmation.

    There is one question.

    Is it OK to understand that a maximum delay of 1 bit occurs when returning from SWRESET as a specification of a device (peripheral)?

    Best regards,

    Koichi