TMS320F28375D: SDRAM burst access

Hi,

My question: is this DMA burst corresponding to the SDRAM burst access?

No, this is different.

If not, is there a way to setup EMIF/DMA to enable the SDRAM burst transfer?

DMA does not have burst access. It's load and store operation.

From my testing result, the current DMA/EMIF setup doesn't seem to enable the SDRAM burst access.

I have an average of 8 cycle per write to SDRAM from internal RAM and 16 cycle per read from SDRAM using DMA.

Is these access cycle number sound reasonable?

That looks ok.

Regards,

Vivek Singh

Thank you Vivek for your response. Could you please elaborate in detail as it is very important.

On the EMIF bus of the Delfino in SDRAM Mode, making use of an SDRAM:

Does the SDRAM Controller in the Delfino make use of the standard burst accesses which are a standard feature of SDRAMs?

Or is every access by the Delfino on EMIF in SDRAM mode only one ‘word’ (in this case perhaps 32 bits wide)?

We are looking to make our transfers of data to the SDRAM more efficient.

If there is no burst accesses of SDRAM on the EMIF bus on the Delfino, can you refer us to the documentation where this is clarified?

If yes, can you help us learn how to make use of the standard burst accesses to the SDRAM?

If it is only available in specific modes (such as ‘Direct’ or ‘DMA’), please help us learn what those are.