• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 81 subscribers
  • Views 204 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28375D: About SDRAM access of TMS320F28375

naoki takahashi
Prodigy 40 points
Part Number: TMS320F28375D
Other Parts Discussed in Thread: C2000WARE

Hi team,

TMS320F28375 is connected to SDRAM (16bit * 2P) and FPGA, and 32bit is connected via EMIF1.
The FPGA side operates normally even if 32 bits are accessed, but the EM1D18-EM1D16 bits are fixed to 0 on the SDRAM side.
(The following is an example of writing all 1 data)
Is there any related place such as register setting of TMS320F28375?

[FPGA]
Address     Data
0x00100000 FFFFFFFF


[SDRAM]
Address     Data
0x80000000 FFF8FFFF




Best regards,

Takahashi

  • +1
    TI__Guru 62975 points

    Takahashi-san,

    There are no EMIF settings that would disable data-bits in this fashion. The working CS2 interface tells us that the EMIF is able to control the signals properly so I think that this is likely a timing issue.

    Please check the GPIO qualifier settings for the GPIO signals (GPxQSELn registers) and make sure that the EMIF signals are configured for Async qualification.

    Also make sure that the EMIF clock is limited to 100-MHz or slower to satisfy the SDRAM maximum operating frequency (PERCLKDIVSEL register).

    If the problem persists, the EMIF timings can be checked against the SDRAM datasheet using the EMIF configuration tool: ~\C2000Ware_XXXX\boards\TIDesigns\F28379D_EMIF_DC\C2000-EMIF_ConfigurationTool.xlsx

    For debug purposes, the timings can be slowed down to the maximum delays allowed by the register fields.

    Some of these points and concepts are also discussed in this EMIF appnote.

    -Tommy