Other Parts Discussed in Thread: TMS320F28035
Hello there,
I have a customer using this device who has been witnessing interesting behavior. What he is seeing is very similar to what is described in the attached from the device's errata but his set-up is a bit different.
The difference is, that he is using the A/D in sequential mode rather than simultaneous. He is finding that at times, the first reading is not accurate – always overstated, often times FFFh. And, if their test method is valid, when an incorrect reading is given, the A/D takes measurably less time to set the busy flag after SOC than when a correct reading is given.
The CPU is at 150mHz and the A/D is at 25mHz with a sample window of 1 (low impedance source). It happens when SOC’d by the EPWM module and by software trigger. He is using the internal reference. It is being supplied at 1.9V / 3.3V. They understand they're pushing the processor to it's limit but historically doing so has given them good results.
The customer is currently using the workaround suggested – just taking an initial conversion and discarding – but he also wants to gain some assurance that there isn’t something else wrong since the operational conditions do not exactly match that given on the errata.
Appreciate any feedback you can provide on this!
-Amanda