TMS320F28335: SCI FIFO Transmission Interrupt

Pavan K H Venkata S S

Part Number: TMS320F28335

I'm referring to the following code corresponding to the SCIA-FIFO-TX interrupt service routine of Example_2833xSci_FFDLB_int.c

__interrupt void sciaTxFifoIsr(void)
{
    Uint16 i;
    for(i=0; i< 8; i++)
    {
     SciaRegs.SCITXBUF=sdataA[i];     // Send data
}

    for(i=0; i< 8; i++)                 //Increment send data for next cycle
    {
     sdataA[i] = (sdataA[i]+1) & 0x00FF;
}

SciaRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}

8-bytes are loaded into SCI TX FIFO, when an interrupt occurs. But when are they sent? After the ISR loop execution or as and when it is loaded? Is each word cleared from FIFO after it is sent?

For the interrupt to occur again (after the flag is cleared), TXFFST <= TXFFIL. After the 8 words are loaded in FIFO, TXFFST=8. But when does TXFFST change to 7, before clearing the flag or after clearing the flag? Let's say one word is sent by the time the interrupt flag is cleared, i.e. TXFFST=7. Therefore the interrupt occurs again. I would like to make sure that an interrupt occurs only after all the 8 words are sent, i.e. when TXFFST=0. How to achieve this?

over 8 years ago

0 Vincent Rodriguez over 8 years ago

TI__Mastermind 28285 points

Pavan,

Whenever your put data into the SCI TX buffer, that information is going to be sent out regardless of what the status of the Interrupt Flag is.

If you want to make sure you fill TX Buffer with all eight 16 bit values, you could theoretically Disable TX for SCI in the beginning of the interrupt and re enable at the end.

also, TXFFSTS is decremented when the data is moved from the FIFO to the transmit shift register

Could you provide more clarity on the last paragraph? would you like a interrupt when the FIFO has less than 8 words and also when the FIFO is at 0?

Hope this helps!

Vince Rodriguez

0 Pavan K H Venkata S S over 8 years ago in reply to Vincent Rodriguez

Prodigy 20 points

Hi Vince.

Thank you very much for your quick reply.

I am referring to the following explanation given in "SPRUFZ5A - TMS320x2833x, 2823x Serial Communications Interface" - Page 35 and Table 2.9
--------------------------------------------------------------------------------------------------------------------------------------------
TXFFIL4–0 Transmit FIFO interrupt level bits. Transmit FIFO will generate interrupt when the FIFO
status bits (TXFFST4–0) and FIFO level bits (TXFFIL4–0 ) match (less than or equal to).
Default value should be 0x00000.
--------------------------------------------------------------------------------------------------------------------------------------------
I understood the above statement as: when TXFFST<= TXFFIL, an interrupt occurs (of course, with the interrupt flag cleared). Am I correct?

Let's consider the case when TXFFIL=01000 (8). TXFFST will be initially 0, since there are no words in TXFIFO buffer. An interrupt occurs (0<8) and the interrupt service routine (ISR) is executed. In the ISR, 8 words are loaded into TXFIFO buffer using the 'for' loop.

The data is incremented, the interrupt flag is cleared and the interrupt is acknowledged.

I am interested to know when would the interrupt occur again. Here's my understanding. Please correct me if I'm wrong.

What would be the value of TXFFST when the interrupt flag is cleared? It depends on the bytes that were transferred. Let's say only one word is sent by that time, => TXFFST=7. Or if two words are sent, TXFFST=6. In either case, the interrupt will occur immediately after execution comes out of ISR. But, I would like to make sure that all the 8 words are sent before the interrupt occurs again, i.e. I want the interrupt to occur only when TXFFST=0.

In EPWM interrupts, we have a provision to select the instant at which the interrupt occurs, for example, when the counter equals period, or zero, or both, and so on..

Similarly, is there a way to select the instant at which the SCITX or SCIRX interrupt occurs?

Thanks and regards,
Pavan.

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TMS320F28335: SCI FIFO Transmission Interrupt