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TMS320F28377S: PWMxA output pulse when CMPA is greater than TBPRD

Jordan Zhou
Genius 9730 points
Part Number: TMS320F28377S

Hi,

Customer faced one issue about PWM when CMPA is greater than TBPRD.

1) Up down mode;

2) Period is 2222;

3) CMPA is updated by shadow register, when CTR=Zero and CTR=PRD.

CMPA is increased from 0, by 10 each period. So CMPA will be 0, then 10, 20, 30 and so on.

When CMPA increases, the PWM duty increases too. After CMPA is loaded with 2220, there's a toggle in yellow line. At that moment, PWM works fine. In the next CTR==PRD, 2220 is loaded to CMPA by shadow. In the next cycle, CMPA is loaded with 2230, there's another toggle in yellow line. In the next CTR==PRD, 2230 is loaded to CMPA. After that, PWM should output High as before, but there's one period Low. We'd like to know why. If 2222 is loaded instead of 2230, there's no this kind of issue.

In the oscilloscope, there's a delay of the 22us low in green line. As we delay the load of 2230 one period cycle.

Thanks a lot.

Br, Jordan

  • 0
    Guru 192875 points
    Hi Jordan,

    This behaviour is well documented in ePWM section of TRM. Also, refer this thread :
    e2e.ti.com/.../123483

    Regards,
    Gautam
  • 0 in reply to Gautam Iyer
    TI__Genius 9730 points
    Gautam,
    Thanks for your info.
    But, that is for Piccolo, instead of F28377S.
    For F28377S, it should be available to access 0% and 100% directly by setting CMPA to Zero or Period.
    Br, Jordan
  • 0 in reply to Jordan Zhou
    TI__Genius 15260 points

    Hi Jordan,

    What are the settings for your action qualifier? Please provide what happens on the following events (output set high, low, or nothing):

    CTR = 0
    CTR = CMPA
    CTR = CMPB
    CTR = PRD

    If you can copy and paste your initialization code that will be helpful as well.

    Regards,
    Kris

  • 0 in reply to Kris Parrent
    TI__Genius 9730 points
    Kris,
    Here's the code:
    EPwm2Regs.TBPRD = PWMPERIOD; // Set timer period 45kHz TBCLKs
    EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
    EPwm2Regs.TBCTR = 0x0000; // Clear counter
    //Set Compare values
    EPwm2Regs.CMPA.bit.CMPA =1; // Set compare A value
    EPwm2Regs.CMPB.bit.CMPB =1; // Set Compare B value
    //Setup counter mode
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and douwn
    EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    //Setup shadowing
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // Load on Zero and Period
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
    //Setup DB
    EPwm2Regs.DBCTL.bit.IN_MODE=0;
    EPwm2Regs.DBCTL.bit.POLSEL=2;
    EPwm2Regs.DBCTL.bit.OUT_MODE=3;
    //EPwm2Regs.DBFED.bit.DBFED=0;
    //EPwm2Regs.DBRED.bit.DBRED=50; //200=1us
    //Set actions
    EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up // count
    EPwm2Regs.AQCTLA.bit.CAD =AQ_CLEAR; // Clear PWM1A on event A,// down count
    EPwm2Regs.AQCTLB.bit.CBU =AQ_SET; // Set PWM1B on event B, up// count
    EPwm2Regs.AQCTLB.bit.CBD =AQ_CLEAR; // Clear PWM1B on event B,// down count

    EPwm2Regs.AQSFRC.bit.RLDCSF =3;

    //EPWM SOC setup
    EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
    EPwm2Regs.ETSEL.bit.SOCASEL = 3; // Select SOC on zero or period
    EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event

    // Interrupt where we will change the Compare Values
    EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
    EPwm2Regs.ETSEL.bit.INTEN = 0; // Disable INT
    EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
    //Set TZ
    //EPwm2Regs.TZSEL.bit.OSHT1 = 1;//单次TZ后，不能清
    EALLOW;
    EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_HI;
    EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_HI;
    EDIS;

    Br, Jordan
  • 0 in reply to Jordan Zhou
    TI__Genius 15260 points

    Hi Jordan,

    If the shadow->active load is taking effect on CTR=0, then the last CMPA event would have been CAD which clears the PWM. When the shadow value of CMPA > PRD is loaded in for the next cycle, CAU will never be reached to set the PWM high again. This is why you are seeing the low pulse.

    Does that answer the question?

    Regards,

    Kris

  • 0 in reply to Kris Parrent
    TI__Genius 9730 points
    Kris,
    Let me try and reply you.
    Thanks a lot.
    Br, Jordan