- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
The reason why I’m writing to you is a problem which we observed when using HRPWM and we are not sure what’s causing this:
In this project we are using the microprocessor TMX320F28377D from Texas Instruments.
The PWM modules are clocked with 100 MHz and the PWMs are running at a frequency of 50 kHz (TBPRD = 1000) in “Up-Down Counter Mode”.
It is necessary to have a high resolution duty cycles of the PWMs.
The actual PWM configuration can be seen in the attached file EPwm1Regs_CMPA_0x03E60000_Export.txt (only EPwm1 is configured).
The actual problem which we observed and where we would need help from TI to understand it and ideally to solve it is the following:
Due to HRPWM support we can precisely set the duty of the PWM cycle from 0 to 99.7999% (EPwm register CMPA= from 0x0 to 0x03E5FF00). However, if CMPA=0x03E60000 (precisely at 99.8%) we get a duty of 50% rather than the desired one.
When increasing the value of the register CMPA to 0x03E60100 (i.e. the next possible duty) then the duty is OK again (approx. 99.8005%).
So, only if the CMPA register is set to 0x03E60000, the problem occurs (we get a duty of 50% rather than the desired one).
At a first glance we think we are facing this problem because the falling edge of the duty is in critical proximity to 3 clocks at the end of the PWM cycle.
Attached are three oscilloscope pictures. Each picture shows the PWM which is created by the equivalent value of the CMPA register.
The attached .pdf file summarizes the three CMPA values.
Short summary of the PWM configuration:
PWM modules are clocked with 100 MHz.
Each PWM has a frequency of 50 kHz.
The PWMs are configured for Up-Down Counter Mode and have a Dead Band of 100 ns on both sides.
TBCTL:
PWM_TBCTL_FREE_SOFT(PWM_TBCTL_FREE_SOFT_STOP_AT_END_CYCLE)
PWM_TBCTL_PHSDIR(PWM_TBCTL_PHSDIR_DOWN)
PWM_TBCTL_CLKDIV(PWM_TBCTL_CLKDIV_DIV1)
PWM_TBCTL_HSPCLKDIV(PWM_TBCTL_HSPCLKDIV_DIV1)
PWM_TBCTL_SWFSYNC(ON)
PWM_TBCTL_SYNCOSEL(PWM_TBCTL_SYNCOSEL_DISABLED)
PWM_TBCTL_PRDLD(PWM_TBCTL_PRDLD_SHADOW)
PWM_TBCTL_PHSEN(OFF)
PWM_TBCTL_CTRMODE(PWM_TBCTL_CTRMODE_UP_DOWN)
AQCTLA:
PWM_AQCTLA_CBD = DISABLED
PWM_AQCTLA_CBU = DISABLED
PWM_AQCTLA_CAD = SET
PWM_AQCTLA_CAU = CLEAR
PWM_AQCTLA_PRD = DISABLED
PWM_AQCTLA_ZRO = SET
The HRPWM registers are configured as follows.
HRPCTL:
PWM_HRPCTL_PWMSYNCSELX(0U)
PWM_HRPCTL_TBPHSHRLOADE(OFF)
PWM_HRPCTL_PWMSYNCSEL(OFF)
PWM_HRPCTL_HRPE(ON)
HRCNFG:
PWM_HRCNFG_HRLOADB(LOAD_ON_ ZERO_PRD)
PWM_HRCNFG_CTLMODEB(SEL_CMPHR_OR_TBPRDHR)
PWM_HRCNFG_EDGEMODEB(BOTH)
PWM_HRCNFG_SWAPAB(PWMA_PWMB_UNCHANGED)
PWM_HRCNFG_AUTOCONV(ENABLE)
PWM_HRCNFG_SELOUTB(EPWMXB_OUT_NORMAL)
PWM_HRCNFG_HRLOAD(LOAD_ON_ZERO_PRD)
PWM_HRCNFG_CTLMODE(SEL_CMPHR_OR_TBPRDHR)
PWM_HRCNFG_EDGEMODE(BOTH)
The MEP_ScaleFactor is calculated once by the SFO() function (after the PWMs are configured and prior to setting TBCLKSYNC to 1).
Many thanks in advance for your support.
Attachments:
Picture1: Oscilloscope screenshot when CMPA=0x03E5FF00
Picture2: Oscilloscope screenshot when CMPA=0x03E60000
Picture3: Oscilloscope screenshot when CMPA=0x03E60100
