TMS320F28377D: HRPWM Using CMPA and CMPB

This has me a bit befuddled, and I will try to keep it concise, if you need any more information let me know. Thanks for your help.

I am using a EPWM in High Resolution Mode. The EPWM is setup in up count and uses CMPA for one trigger and CMPB for the other trigger. I have been comparing one EPWM with another (5&6) and getting some pretty strange results Dead Time is not used here just to make sure something is not getting messed up there. I have looked at the EPWM registers and they look correct. For EPWM1 CALPWRON is set to 1 and the HRMSTEP is 67 (all other EPWM's are 0)  I use EPWM5 as a reference, then compare the rising edge of the B channel (lower switch) controlled by CMPA to the same in EPWM6. This is also done with the falling edge. EPWM clock is 100 MHz. 

As you can see in the following data, the falling delay vs CMPA is as if the High Resolution is not active.

However, the Rising Edge delay vs CPMB looks like it is working fine, but appears there is some interaction with the falling edge, very strange.

I have several screen shots I could share, but not sure how to do that.

Here is the setup code

    //##########  EPWM5
    EALLOW;
    // Assumes ePWM clock is already enabled
    EPwm5Regs.TBPRD                 =   PWM_TBPRD;          // Set period for ePWMx
    EPwm5Regs.TBCTR                 =   0x0000;             // Clear counter
    EPwm5Regs.TBCTL.bit.CLKDIV      =   TB_DIV1;            // Time-base Clock Prescale Bits
    EPwm5Regs.TBCTL.bit.HSPCLKDIV   =   TB_DIV1;            // High-Speed Time-base Clock Prescale Bits
    EPwm5Regs.TBCTL.bit.SYNCOSEL    =   TB_SYNC_IN;         // EPWMx is a "slave", sync flow-through
    EPwm5Regs.TBCTL.bit.PHSEN       =   TB_ENABLE;          // EPWMx is a "slave", Load the time-deg counter from TBPHS at sync
    EPwm5Regs.TBPHS.bit.TBPHS       =   0x0000;             // Initialize Phase Shift
    EPwm5Regs.TBCTL.bit.CTRMODE     =   TB_COUNT_UP;        // Up Count Mode
    EPwm5Regs.CMPA.bit.CMPAHR       =   0;                  // initialize HRPWM extension
    EPwm5Regs.CMPB.bit.CMPBHR       =   0;                  // initialize HRPWM extension
    EPwm5Regs.CMPCTL.bit.SHDWAMODE  =   CC_SHADOW;          //  CmpA Shadow Mode
    EPwm5Regs.CMPCTL.bit.SHDWBMODE  =   CC_SHADOW;          //  CmpB Shadow Mode
    EPwm5Regs.CMPCTL.bit.LOADBMODE  =   CC_CTR_ZERO;        // Load at bottom of the carrier (for up count)
    EPwm5Regs.CMPCTL.bit.LOADAMODE  =   CC_CTR_ZERO;        // Load at bottom of the carrier (for up count)

    // Set up compares for A and B compare registers
    EPwm5Regs.AQCTLA.bit.CAU        =   AQ_SET;             // Turn on upper switch at compare A up
    EPwm5Regs.AQCTLA.bit.CBU        =   AQ_CLEAR;           // Turn off upper switch at compare B up
    EPwm5Regs.AQCTLB.bit.CAU        =   AQ_CLEAR;           // Turn off lower switch at compare A up
    EPwm5Regs.AQCTLB.bit.CBU        =   AQ_SET;             // Turn on  lower switch at compare B up

//    EPwm5Regs.TZSEL.bit.OSHT1       =   0;                  // Disable TZ1 as one one-shot trip source
    EPwm5Regs.TZSEL.bit.OSHT1       =   1;                  // Enable TZ1 as one one-shot trip source
//    EPwm5Regs.TZSEL.bit.OSHT2       =   0;                  // Disable TZ2 as one one-shot trip source
    EPwm5Regs.TZSEL.bit.OSHT2       =   1;                  // Enable TZ2 as one one-shot trip source
//    EPwm5Regs.TZSEL.bit.OSHT3       =   0;                  // Disable TZ3 as one one-shot trip source
    EPwm5Regs.TZSEL.bit.OSHT3       =   1;                  // Enable TZ3 as one one-shot trip source
    EPwm5Regs.TZSEL.bit.OSHT6       =   1;                  // Enable TZ6 as one-shot trip source, to prevent shoot-through during emulation stop (pause,reset, reprogram)
    EPwm5Regs.TZCTL.bit.TZA         =   TZ_FORCE_LO;        // TZ1 forces A output lo
    EPwm5Regs.TZCTL.bit.TZB         =   TZ_FORCE_LO;        // TZ1 forces B output lo
    EPwm5Regs.TZEINT.bit.OST        =   1;                  // Enable TZ interrupt

    EPwm5Regs.HRCNFG.all            = 0x0;                  // Reset HRCNFG
    EPwm5Regs.HRCNFG.bit.EDGMODE    = HR_BEP;   //HR_REP;   //HR_FEP;               // MEP control on falling edge  DAP
    EPwm5Regs.HRCNFG.bit.EDGMODEB   = HR_BEP;   //HR_FEP;   //HR_REP;               // MEP control on rising edge   DAP
    EPwm5Regs.HRCNFG.bit.HRLOAD     = HR_CTR_ZERO;          // Load at bottom of the carrier (for up count)
    EPwm5Regs.HRCNFG.bit.HRLOADB    = HR_CTR_ZERO;          // Load at bottom of the carrier (for up count)
    EPwm5Regs.HRCNFG.bit.AUTOCONV   = 0x1;                  // Enable automatic scaling of CMPAHR based on MEP_ScaleFactor. With this enabled, CMPAHR is simply [0x0000 0xFF00].
    EDIS;

    //##########  EPWM6
    EALLOW;
    // Assumes ePWM clock is already enabled
    EPwm6Regs.TBPRD                 =   PWM_TBPRD;          // Set period for ePWMx
    EPwm6Regs.TBCTR                 =   0x0000;             // Clear counter
    EPwm6Regs.TBCTL.bit.CLKDIV      =   TB_DIV1;            // Time-base Clock Prescale Bits
    EPwm6Regs.TBCTL.bit.HSPCLKDIV   =   TB_DIV1;            // High-Speed Time-base Clock Prescale Bits
    EPwm6Regs.TBCTL.bit.SYNCOSEL    =   TB_SYNC_IN;         // EPWMx is a "slave", sync flow-through
    EPwm6Regs.TBCTL.bit.PHSEN       =   TB_ENABLE;          // EPWMx is a "slave", Load the time-deg counter from TBPHS at sync
    EPwm6Regs.TBPHS.bit.TBPHS       =   0x0000;             //Initialize phase shift
    EPwm6Regs.TBCTL.bit.CTRMODE     =   TB_COUNT_UP;        // Up Count Mode
    EPwm6Regs.CMPA.bit.CMPAHR       =   0;                  // initialize HRPWM extension
    EPwm6Regs.CMPB.bit.CMPBHR       =   0;                  // initialize HRPWM extension
    EPwm6Regs.CMPCTL.bit.SHDWAMODE  =   CC_SHADOW;          //  CmpA Shadow Mode
    EPwm6Regs.CMPCTL.bit.SHDWBMODE  =   CC_SHADOW;          //  CmpB Shadow Mode
    EPwm6Regs.CMPCTL.bit.LOADBMODE  =   CC_CTR_ZERO;        // Load at bottom of the carrier (for up count)
    EPwm6Regs.CMPCTL.bit.LOADAMODE  =   CC_CTR_ZERO;        // Load at bottom of the carrier (for up count)

    // Set up compares for A and B compare register
    EPwm6Regs.AQCTLA.bit.CAU        =   AQ_SET;             // Turn on upper switch at compare A up
    EPwm6Regs.AQCTLA.bit.CBU        =   AQ_CLEAR;           // Turn off upper switch at compare B up
    EPwm6Regs.AQCTLB.bit.CAU        =   AQ_CLEAR;           // Turn off lower switch at compare A up
    EPwm6Regs.AQCTLB.bit.CBU        =   AQ_SET;             // Turn on lower switch at compare B up

//    EPwm6Regs.TZSEL.bit.OSHT1       =   0;                  // Disable TZ1 as one one-shot trip source
    EPwm6Regs.TZSEL.bit.OSHT1       =   1;                  // Enable TZ1 as one one-shot trip source
//    EPwm6Regs.TZSEL.bit.OSHT2       =   0;                  // Disable TZ2 as one one-shot trip source
    EPwm6Regs.TZSEL.bit.OSHT2       =   1;                  // Enable TZ2 as one one-shot trip source
//    EPwm6Regs.TZSEL.bit.OSHT3       =   0;                  // Disable TZ3 as one one-shot trip source
    EPwm6Regs.TZSEL.bit.OSHT3       =   1;                  // Enable TZ3 as one one-shot trip source
    EPwm6Regs.TZSEL.bit.OSHT6       =   1;                  // Enable TZ6 as one-shot trip source, to prevent shoot-through during emulation stop (pause,reset, reprogram)
    EPwm6Regs.TZCTL.bit.TZA         =   TZ_FORCE_LO;        // TZ1 forces A output lo
    EPwm6Regs.TZCTL.bit.TZB         =   TZ_FORCE_LO;        // TZ1 forces B output lo
    EPwm6Regs.TZEINT.bit.OST        =   1;                  // Enable TZ interrupt

    EPwm6Regs.HRCNFG.all            = 0x0;                  // Reset HRCNFG
    EPwm6Regs.HRCNFG.bit.EDGMODE    = HR_BEP;   //HR_REP;   //HR_FEP;               // MEP control on falling edge   DAP
    EPwm6Regs.HRCNFG.bit.EDGMODEB   = HR_BEP;   //HR_FEP;   //HR_REP;               // MEP control on rising edge   DAP
    EPwm6Regs.HRCNFG.bit.HRLOAD     = HR_CTR_ZERO;          // Load at bottom of the carrier (for up count)
    EPwm6Regs.HRCNFG.bit.HRLOADB    = HR_CTR_ZERO;          // Load at bottom of the carrier (for up count)
    EPwm6Regs.HRCNFG.bit.AUTOCONV   = 0x1;                  // Enable automatic scaling of CMPAHR based on MEP_ScaleFactor. With this enabled, CMPAHR is simply [0x0000 0xFF00].
    EDIS;

Here are the results, I tried attaching the graphs but not much luck.