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I am trying to implement a serial communication interface where the command comes in with an address/data indicator in the 9th bit (i.e. high for the first word of a message and low for all subsequent words of the message) but the response needs to implement parity in the 9th bit. I don't see independent enable of parity on TX/RX nor for independent enable of address mode. Have read through chapter 19 of SPRUHM8F and examined registers to see if there is an option. All that I can think to do is use one SCI configured for no parity (SCICCR.PARITYENA=0), address/idle mode enabled for address bit (SCICCR.ADDRIDLE_MODE=1) to receive my command and a separate SCI configured for parity (SCICCR.PARITYENA=1), address/idle mode disabled (SCICCR.ADDRIDLE_MODE=0) to transmit my response. Is there a more elegant way that I am missing? Thanks!
