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TMS320F28374S: VDDIO/VDD(3.3V/1.2V） Power Sequence related issues

Benjamin Zhou
Expert 4000 points
Part Number: TMS320F28374S

Hi Team,

   According to the TMS320F28374s Power sequence,  the VDDIO 3.3V should always >= VDD1.2V power rails and should powered up at 10ms;  some confusion still confused the customer usage:

  1)  My customer first powered up VDDIO 3.3V power rail and limited at 10ms,  then delayed for about >10ms, the VDD 1.2V powered up within the 10ms;   would this affect the TMS320F28374s usage?

  2) In some cases, during the usage, the VDDIO dropped to 0V（VDD  kept as 1.2V)   or VDD dropped to 0V(VDDIO kept as 3.3V),  would this situation affect the TMS320F28374s usage?

Expect for your reply, thanks.

Best Regards

Benjamin

  • 0
    TI__Genius 15385 points
    Benjamin,

    As per the spec, all the supplies should get powered up within 10 ms, so if the customer is ramping up VDD after 10ms of VDDIO powered up then it is violating the spec and not recommended.

    Also, if you look at the below statement in the spec, it is not recommended to drop VDDIO voltage below VDD more than 0.3V.

    The voltage on VDDIO should be greater than VDD or no less than 0.3 V below VDD at all times. VDDIO, VDD3VFL, VDDOSC, and VDDA should be powered up together and be kept within 0.3 V of each other during operation. Before powering the device, no voltage larger than 0.3 V above VDDIO should be applied to any digital pin, and no voltage larger than 0.3 V above VDDA should be applied to any analog pin. The VREFHI voltage should not exceed VDDA at any time.

    Regards,
    Nirav