Tool/software: Code Composer Studio
I am using a f28377s Launch Pad as an SPI-slave with fifo enabled. I am able to correctly receive incoming messages, they are however being looped back to SOMI with a two byte delay, even though the SPITXBUF is never actively written to and SPILBK is disabled. Am I wrong in assuming that this behavior is unusual? Also actively writing to SPITXBUF is ignored while data written to SPIDAT is correctly transmitted. At the moment I'm unable to explain this behavior.
Does anyone here know what could be going on?
The SPI is configured in the following way:
SpibRegs.SPICCR.bit.SPISWRESET = 0; SpibRegs.SPICCR.bit.CLKPOLARITY = 0; SpibRegs.SPICCR.bit.SPILBK = 0; SpibRegs.SPICCR.bit.SPICHAR = 0x7; SpibRegs.SPICTL.bit.CLK_PHASE = 1; SpibRegs.SPICTL.bit.MASTER_SLAVE = 0; SpibRegs.SPICTL.bit.OVERRUNINTENA = 0; SpibRegs.SPICTL.bit.SPIINTENA = 1; SpibRegs.SPICTL.bit.TALK = 1; SpibRegs.SPIRXEMU = 0; SpibRegs.SPIFFTX.bit.SPIFFENA=1; SpibRegs.SPIFFTX.bit.TXFIFO=0; SpibRegs.SPIFFTX.bit.TXFFINTCLR=1; SpibRegs.SPIFFTX.bit.TXFFIENA=1; SpibRegs.SPIFFTX.bit.TXFFIL=4; SpibRegs.SPIFFRX.bit.RXFIFORESET=0; SpibRegs.SPIFFRX.bit.RXFFOVFCLR=1; SpibRegs.SPIFFRX.bit.RXFFINTCLR=1; SpibRegs.SPIFFRX.bit.RXFFIENA=1; SpibRegs.SPIFFRX.bit.RXFFIL=4; SpibRegs.SPIFFRX.bit.RXFIFORESET=1; SpibRegs.SPICCR.bit.SPISWRESET=1; SpibRegs.SPIFFCT.bit.TXDLY=0; SpibRegs.SPIPRI.bit.SOFT=1; SpibRegs.SPIPRI.bit.FREE=1; SpibRegs.SPIPRI.bit.STEINV=0; SpibRegs.SPIPRI.bit.TRIWIRE=0;
Thank you for your help!
Best regards,
Tobi