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CCS/TMS320F28377S: C2000 MCU as SPI-Slave Loops Back Incoming Data With a 2-Byte Delay.

Tobias Schneider92
Prodigy 20 points
Part Number: TMS320F28377S

Tool/software: Code Composer Studio

I am using a f28377s Launch Pad as an SPI-slave with fifo enabled. I am able to correctly receive incoming messages, they are however being looped back to SOMI with a two byte delay, even though the SPITXBUF is never actively written to and SPILBK is disabled. Am I wrong in assuming that this behavior is unusual? Also actively writing to SPITXBUF is ignored while data written to SPIDAT is correctly transmitted. At the moment I'm unable to explain this behavior.

Does anyone here know what could be going on?

The SPI is configured in the following way:

    SpibRegs.SPICCR.bit.SPISWRESET = 0;
    SpibRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpibRegs.SPICCR.bit.SPILBK = 0;
    SpibRegs.SPICCR.bit.SPICHAR = 0x7;

    SpibRegs.SPICTL.bit.CLK_PHASE = 1;
    SpibRegs.SPICTL.bit.MASTER_SLAVE = 0;
    SpibRegs.SPICTL.bit.OVERRUNINTENA = 0;
    SpibRegs.SPICTL.bit.SPIINTENA = 1;
    SpibRegs.SPICTL.bit.TALK = 1;
    SpibRegs.SPIRXEMU = 0;

    SpibRegs.SPIFFTX.bit.SPIFFENA=1;
    SpibRegs.SPIFFTX.bit.TXFIFO=0;
    SpibRegs.SPIFFTX.bit.TXFFINTCLR=1;
    SpibRegs.SPIFFTX.bit.TXFFIENA=1;
    SpibRegs.SPIFFTX.bit.TXFFIL=4;

    SpibRegs.SPIFFRX.bit.RXFIFORESET=0;
    SpibRegs.SPIFFRX.bit.RXFFOVFCLR=1;
    SpibRegs.SPIFFRX.bit.RXFFINTCLR=1;
    SpibRegs.SPIFFRX.bit.RXFFIENA=1;
    SpibRegs.SPIFFRX.bit.RXFFIL=4;
    SpibRegs.SPIFFRX.bit.RXFIFORESET=1;

    SpibRegs.SPICCR.bit.SPISWRESET=1;

    SpibRegs.SPIFFCT.bit.TXDLY=0;

    SpibRegs.SPIPRI.bit.SOFT=1;
    SpibRegs.SPIPRI.bit.FREE=1;
    SpibRegs.SPIPRI.bit.STEINV=0;
    SpibRegs.SPIPRI.bit.TRIWIRE=0;

Thank you for your help!

Best regards,

Tobi

  • 0
    Guru 30330 points

    Tobias,

    This is to be expected. Whatever data is in the SPIDAT will be transmitted. since you are working with bytes, there will be a delay of a few words until the received data makes it back out of the transmit. The following table describes the behavior. Each row represents the status after an action. SIMO is what was recieved, SPIDAT is the status of the register and SOMI is what was transmitted by the slave.

    Time SIMO SPIDAT SOMI
    T0 00 0000 00
    T1 AA 00AA 00
    T2 55 AA55 00
    T3 BB 55BB AA
    T4 66 BB66 55
    T5 CC 66CC BB

    If you do not want any data to be sent by the slave. Set the TALK bit to 0 until you are ready.

    Thanks,
    Mark